ITE Technical Report
Online ISSN : 2424-1970
Print ISSN : 1342-6893
ISSN-L : 1342-6893
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34.29
Displaying 1-29 of 29 articles from this issue
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  • [title in Japanese]
    Article type: Cover
    Pages Cover1-
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_Cover1
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • [title in Japanese]
    Article type: Index
    Pages Toc1-
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_Toc1
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  • On-Chip Waveform Capture and Diagnosis of Power Delivery in SoC Integration
    Takushi HASHIDA, Hiroshi MATSUMOTO, Makoto NAGATA
    Article type: Article
    Session ID: ICD2010-21
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_1
    CONFERENCE PROCEEDINGS FREE ACCESS
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    On-chip waveform capture exhibits the resolution of 10ps and 200μV with 1024 steps, and SFDR of 63.2dB in 700-MHz signal bandwidth of interest. On-chip signal probing as well as digital waveform processing are merged in systems-on-a-chip (SoC) integration. An exciter is combined for on-chip derivation of LCR parasitics from oscillatory waveforms of a power delivery network that are effectively seen by SoC circuits.
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  • Evaluation of algorithms for waveform acquisition in on-chip multi-channel monitoring
    Yuuki ARAGA, Takushi HASHIDA, Makoto NAGATA
    Article type: Article
    Session ID: ICD2010-22
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_5
    CONFERENCE PROCEEDINGS FREE ACCESS
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    Multi-channel waveform monitoring system for large-scale SoCs. The system consists of probing front end circuits and a waveform acquisition kernel. In this paper, we constructed an on-chip waveform capturing system. We evaluated throughput of digitization and linearity of monitor system, which are the most important performance measures. Waveform acquisition at the system throughput of 1.24s/point is achieved by proposed algorithm, demonstrates 60.4dB SFDR, 52.4dB SNDR and 8.4 ENOB at 1Gs/s for 500-MHz bandwidth, and demonstrates measurement of chip temperature by combination of thermal sensor and PFE.
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  • In-situ Evaluation of V_<th> and AC Gain of 90nm CMOS Differential Pair Transistors
    Yoji BANDO, Satoshi TAKAYA, Takashi HASEGAWA, Toru OHKAWA, Masaaki SOU ...
    Article type: Article
    Session ID: ICD2010-23
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_11
    CONFERENCE PROCEEDINGS FREE ACCESS
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    In-situ DC measurements of individual transistors in a differential pair of an analog amplifier derive threshold voltage, V_<th>, of 1.0V transistors in a 90nm CMOS technology. On-chip continuous time waveform monitoring is used to evaluate AC response of the same amplifier. The distribution of AC gain versus V_<th> of transistors within amplifiers is captured. The degradation of common-mode rejection property is observed for an amplifier with intentionally introduced mismatches to the pair of transistors.
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  • Buffer-Ring-Based All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Effect
    Tetsuya IIZUKA, Toru NAKURA, Kunihiro ASADA
    Article type: Article
    Session ID: ICD2010-24
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_15
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    In this paper, we propose an all-digital process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. Using the proposed circuit in combination with a simple ring oscillator which monitors its oscillation period, we can calculate the rise and fall delay values and can monitors the variabilities of PMOS and NMOS devices independently. The experimental results of the circuit simulation on 65nm CMOS process indicate the feasibility of the proposed monitoring circuit. The proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the in-field monitoring of aging effects such as negative/positive bias temperature instability (NBTI/PBTI).
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  • Digital Calibration and Correction Methods for CMOS-ADCs
    Shiro Dosho
    Article type: Article
    Session ID: ICD2010-25
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_21
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    Along with miniaturization of CMOS-LSIs, control methods in the LSIs have been highly developed. The most predominant method is to make observed values digitized as in early stage as possible, and to use digital control methods. Thus many kinds of analog-to-digital converters (ADCs) have been developed such as temperature, time, delay and frequency converters. ADCs are the easiest circuit to introduce digital correction methods because the outputs of these are digital. All sorts of calibration methods were developed and the calibration drastically improved figure of merits by alleviating margins for device variations. These calibration and correction not only overcome circuit's weak points but also gives chance us to develop quite new circuit topologies and systems. In this paper, several techniques of digital calibration and correction for major analog to digital converter are described, such as pipelined ADC, delta-sigma ADC and successive approximation ADC.
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  • A 10b 50MS/s 820μW SAR ADC with Digital Calibration
    Sanroku Tsukamoto
    Article type: Article
    Session ID: ICD2010-26
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_31
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  • Digitally-Assisted Analog Test Technology : Analog Circuit Test Technology in Nano-CMOS Era
    Haruo KOBAYASHI, Takahiro J. YAMAGUCHI
    Article type: Article
    Session ID: ICD2010-27
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_37
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    This paper reviews current production testing issues for analog and mixed-signal SoC, and discusses the following: (i) Digitally-assisted analog technology prevails in mixed-signal SoC with fine CMOS which uses digital-rich architecture, digital self-calibration and error correction, and we consider their effective production testing. (ii) Mixed-signal SoCs frequently incorporate digital resources such as DSP cores and memory. We discuss how such resources can be utilized to simplify production testing of the analog RF circuitry in the SoC.
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  • Technical Trend of Multi-mode Multi-band RF Transceivers
    Hisayasu Sato
    Article type: Article
    Session ID: ICD2010-28
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_43
    CONFERENCE PROCEEDINGS FREE ACCESS
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    This paper describes resent technology trend of multi-mode multi-band RF transceivers. Thanks to advanced CMOS technology, not only single-mode transceivers, but multi-mode transceivers are now put to practical use. Furthermore, software defined radio transceivers which can be applied to many wireless systems are being realized. The evolution of RF transceiver technique is reviewed, and some multi-mode, multi-band transceivers are discussed including the technique to eliminate external components.
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  • A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter
    Tadashi MAEDA, Takashi TOKAIRIN, Masaki KITSUNEZUKA, Mitsuji OKADA, Mu ...
    Article type: Article
    Session ID: ICD2010-29
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_49
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    A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a 2-step structure with an inverter- and a vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of -105dBc/Hz, where the loop-bandwidth is set to 500kHz with a 40-MHz reference signal, and out-band noise of -115dBc/Hz at a 1-MHz offset frequency. The chip core occupies 0.37mm^2 and the measured power consumption is 8.1mA from a 1.2-V power supply.
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  • Implementation and Evaluation of a CMOS Subthreshold Analog Amplifier using 0.5V Power Supply
    Tomochika HARADA
    Article type: Article
    Session ID: ICD2010-30
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_55
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    In this paper, an 0.5V analog amplifier circuit using only sub-μA order subthreshold current for realizing ultra-low power analog/digital LSI system by using low output power supply, such as a battery, solar cell, and MEMS type power plant, is presented. In this circuit, it is designed and fabricated using double-well or triple-well structure 65nm CMOS process, and this circuit is estimated for subthreshold analog circuit characteristics and circuit design using body effect and the other short channel effect in subthreshold region.
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  • OTA Design Using g_m/I_D Lookup Table Methodology : Design optimization featuring Settling Time analysis
    Toru KASHIMURA, Takayuki KONISHI, Shoichi MASUI
    Article type: Article
    Session ID: ICD2010-31
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_61
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    Settling Time is a primary design parameter in operational transconductance amplifiers (OTAs) used for high-speed applications such as pipeline A/D converters. For scaled CMOS technologies, an OTA design methodology using g_m/I_D lookup tables has been proposed to minimize its power consumption. A major problem in the conventionally proposed method is that Settling Time was not included in a target specification, but was converted into crossover frequency f_c with an empirical approach. In this paper, we introduce an iterative optimization sequence to design OTAs, which can achieve the target Settling Time with the minimum power consumptions.
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  • Considerations of a Common-mode Feedback Circuit in the CMOS Inverter-based Differential Amplifier
    Masayuki UNO
    Article type: Article
    Session ID: ICD2010-32
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_67
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    Push-pull CMOS inverter is effective for high-speed, low-power operations, but it has poor CMRR and PSRR characteristics. Common-mode feedback circuits with transistor-pairs operating triode-region is implemented in the push-pull CMOS pseude-differential amplifier. SPICE simulations indicate improvement of CMRR and PSRR. A single common-mode feedback circuit in the push-pull CMOS differential amplifier is also effective. It suppresses the common-mode offset voltage caused by charge injection of switch transistors in the comparator using push-pull CMOS differential amplifiers.
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  • The Design of a Highly Linearized Gm Amplifier by Adopting the Positive Feedback Compensation Scheme and its Application to High-Frequency Filters
    Yusuke SHIMOYAMA, Yasuhiro SUGIMOTO
    Article type: Article
    Session ID: ICD2010-33
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_73
    CONFERENCE PROCEEDINGS FREE ACCESS
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    In order to alleviate the design criteria such that the input dynamic range becomes small and that the amplifier gain can not be high because of the low output impedance of transistors in circuits in sub-100nm LSI process, we propose the use of the positive feedback to enhance the linearity of circuits. The 2^<nd> order low-pass filter was designed by adopting the scheme and realized the high-performance.
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  • On-chip background calibration of time-interleaved ADC
    Takashi Oshima, Tomomi Takahashi
    Article type: Article
    Session ID: ICD2010-34
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_79
    CONFERENCE PROCEEDINGS FREE ACCESS
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    An extremely-high-speed high-resolution time-interleaved ADC is a key enabler of the next-generation applications. The gain, offset and sampling-timing mismatches among unit ADCs of a time-interleaved ADC are compensated by the proposed background calibration, which is simple enough to be implemented on a single chip.
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  • An A/D converter with a built-in variable gain amplifier for CMOS Image Sensors
    Tetsuya IIDA, Tomoyuki AKAHORI, Mohd Amrallah Bin Mustafa, Keita Yasut ...
    Article type: Article
    Session ID: IST2010-36
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_85
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    In this article, an A/D converter with a built-in variable gain amplifier (VGA) for CMOS image sensors is reported. The A/D converter with the VGA is based on a charge-conservation type cyclic A/D converter. The gain of the VGA can be chosen from 1,2,4 and 8. The measurement results of the prototype chip show that the gain errors of the VGA is less than 0.16%. The non-linearity error of the A/D converter is reduced as the gain increases. For the gain of 1 in the VGA 1, the differential non-linearity (DNL), integral non-linearity (INL) and the noise level are (+0.49,-1.4), (+3.8,-4.5), and 196μVrms, respectively, whilst the DNL, INL and noise level for the VGA gain of 8 are (+0.06,-0.18), (+0.38,-0.77), and 120μVrms, respectively.
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  • High-Speed Ramp-Wave Generator with Interleaved DAC for Single-Slope ADC
    Yukinobu MAKIHARA, Mhun SHIN, Masayuki IKEBE, Junichi MOTOHISA, Eiichi ...
    Article type: Article
    Session ID: IST2010-37
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_89
    CONFERENCE PROCEEDINGS FREE ACCESS
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    We have proposed the method of re-measuring quantizing error of Single-Slope ADC for CMOS imager with TDC (Time-to-Digital Converter). Using n-bits TDC, the proposed ADC performed 2^n time faster operation. This method requires high-speed Ramp wave generation. Therefore, in this paper, we evaluated speed up with interleave operation and output summing of DACs. Although multiple DACs are used, there is no increase of quantization unit devices. In the interleaved DAC with 2^<n-m> of m-bits DACunits, it can perform as a Delta DAC (-2^1≦ΔVout≦2^<m-1>). We designed the current-controlled DAC circuits using 0.25um CMOS process. At 200-MHz-clock operation, we confirmed 800-MHz 12-bit operations with four of 10-bits DACunits.
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  • An All-Digital and Scalable Time-Mode A/D Converter TAD : Challenge for Sensor Circuit Digitalization
    Takamoto WATANABE
    Article type: Article
    Session ID: IST2010-38
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_95
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    In recent years, sensor technology has become one of the most important and critical items for many sophisticated systems such as various mobile devices, audio/visual and household-electrical appliances, medical and biological equipment, and especially booming robot systems. In these domains sensors must deliver higher performance, be more compact, less expensive, and more reliable, and these requirements grow stronger by the day. Moreover, with the explosive growth in the number of sensors in systems, there is a great demand for sensor low-power consumption and sensor networks. Accordingly, the most effective solution must be sensor digitalization for any and all sensors as a whole. However, many sensors still remain as an analog method. The reason is that conventional types of ADCs are not very appropriate for universal sensor applications. We have therefore developed an all-digital A/D converter TAD (Time A/D converter) with a scalable time-mode method. This paper describes the following: The TAD operation principle and its circuit structure, evaluation results, sensor application examples, and scaling effects and possibilities with 65nm-CMOS TAD. Finally, multi-functionality based on time-mode construction is discussed.
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  • TDC and SOI Radiation Image Sensor for Particle Physics
    Yasuo ARAI
    Article type: Article
    Session ID: IST2010-39
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_101
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    We have been developing readout electronics and semiconductor detectors for high-energy accelerator experiments. Development of TDC LSI and SOI pixel detector are shown.
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  • Low-Noise Readout Circuits with a Response Time Acceleration Technique
    Kamel MARS, Shoji KAWAHITO
    Article type: Article
    Session ID: IST2010-40
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_107
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    A low noise high-gain readout circuit for high output impedance sensors with a response time acceleration technique is presented. First a circuit analysis is done to determine the condition for designing a low noise readout circuit, and then the readout circuit is optimized to reduce the total input referred noise. If the sensor output has high impedance, the circuit response time is large to achieve the low noise requirement. A new technique for response time acceleration is presented making the circuit response time faster white keeping the noise level unaffected.
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  • Design and Development of Polarization-Analyzing Image Sensor using 65nm CMOS Process
    Sanshiro Shishido, Toshihiko Noda, Kiyotaka Sasagawa, Takashi Tokuda, ...
    Article type: Article
    Session ID: IST2010-41
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_111
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    To realize a miniaturization of sensor chip for μTAS, we propose a polarization analyzing image sensor as a function in μTAS using 65nm CMOS process for the first time. We describe the design details and characterization of our proposed CMOS image sensor. By the fabricated sensor, polarization characteristics are successfully measured.
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  • User Customizable Logic Paper with 2V Organic CMOS and Ink-Jet Printed Interconnects
    Koichi ISHIDA, Naoki MASUNAGA, Ryo TAKAHASHI, Tsuyoshi SEKITANI, Shige ...
    Article type: Article
    Session ID: ICD2010-35
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_115
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    We propose a User Customizable Logic Paper (UCLP), which is suitable for the prototyping of large-area electronics with a sensor array. The UCLP consists of a Sea-of-Transmission-Gates (SOTG) of 2V organic CMOS transistors and printed interconnects with at-home ink-jet printers. The UCLP enables users to fabricate custom integrated circuits.
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  • Self-Dithered Digital Delta-Sigma Modulators for Fractional-N Frequency Synthesizers
    Zule Xu, Jun Gyu Lee, Shoichi Masui
    Article type: Article
    Session ID: ICD2010-36
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_121
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    Digital delta-sigma modulators applied in fractional-N frequency synthesizers suffer from spurious tones which undermine the synthesizer's spectral integrity. Major conventional solutions include initial condition setup, structural modification, and dithering. For the first one the effectiveness is limited, while for the latter two, extra design effort and hardware overhead are required. In this paper, we propose a novel dithering method with simple implementation and no hardware overhead while achieving effective spur elimination. This method is implemented on MASH and single-loop DDSMs. Simulation results compared with conventional solutions prove its effectiveness.
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  • A Study of Simulation Methodologies to Simulate the Buck and Boost DC-DC Converters in High-Speed
    Masahiro SUZUKI, Syoko SUGIMOTO, Yasuhiro SUGIMOTO
    Article type: Article
    Session ID: ICD2010-37
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_127
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    As the DC-DC converter is a mixed system of analog and digital functions, it is hard to simulate its transient responses and frequency characteristics in high-speed by utilizing the analog circuit simulator such as SPICE. We propose the use of the behavioral simulation program by incorporating the non-linear equations and feed-back loops, those of which are formulated based on the actual circuit behavior.
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  • Level Converter Circuit for Low Voltage Digital LSIs
    Yuji OSAKI, Tetsuya HIROSE, Nobutaka KUROKI, Masahiro NUMA
    Article type: Article
    Session ID: ICD2010-38
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_133
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    Supply voltage scaling in accordance with device scaling has achieved low power dissipation of CMOS LSIs. Because each circuit block in an LSI requires suitable supply voltages, the large voltage gap between each circuit block makes it hard to convert signals between circuit blocks. Therefore, a level converter to solve this problem is a key component for low-voltage LSIs. In this paper, a level converter tolerant to large suply-voltages-gap has been deveolped in a 0.35-μm CMOS process. It can achieve low power operation because it dissipates supply current only when the input signal changes. Measurement results showed that the level converter transformed sinals of 0.4V to 3V.
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  • [title in Japanese]
    Article type: Appendix
    Pages App1-
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_App1
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • [title in Japanese]
    Article type: Appendix
    Pages App2-
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_App2
    CONFERENCE PROCEEDINGS FREE ACCESS
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  • [title in Japanese]
    Article type: Appendix
    Pages App3-
    Published: July 22, 2010
    Released on J-STAGE: September 21, 2017
    DOIhttps://doi.org/10.11485/itetr.34.29.0_App3
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