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Article type: Cover
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Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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Article type: Index
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Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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Seiji TANAKA, Noriko KAWAMURA, Masaya TAMARU
Article type: Article
Session ID: IST2012-6/CE2012-18
Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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Inspired by the grain structure of silver halide film, we developed a new image sensor "X-Trans CMOS" which can reduce "color moire" caused by single plane image sensor. The color filter array of this new image sensor has higher non-periodicity than conventional image sensors. It brings less color moire, and the new image sensor doesn't need optical low pass filters which decrease the resolution.
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Yusuke OIKE, Abbas EL GAMAL
Article type: Article
Session ID: IST2012-7/CE2012-19
Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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A 256x256 CMOS imager with column-parallel ΔΣADCs and built-in single-shot compressed sensing performed during A/D conversion is fabricated in 0.15μm CIS process. Compression ratios of 1/4, 1/8, and 1/16 can be programmably achieved at 480, 960, and 1920fps, respectively, with the same readout noise of 351μV_<rms> and power consumption of 96.2mW as normal 120fps capture and with minimal die area overhead. Image reconstruction performed off-chip shows modest quality loss relative to normal capture.
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Yasuhisa Tochigi, Katsuhiko Hanzawa, Yuri Kato, Rihito Kuroda, Hideki ...
Article type: Article
Session ID: IST2012-8/CE2012-20
Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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A 400^H×250^V pixels global shutter CMOS image sensor including 128 on-chip memories for each pixel has been designed and fabricated. This CMOS image sensor achieves both 1Tpixel/s burst video operation without active cooling and 780Mpixel/s continuous video operation on the same chip.
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Masaki SAKAKIBARA, Yusuke OIKE, Takafumi TAKATSUKA, Akihiko KATO, Kats ...
Article type: Article
Session ID: IST2012-9/CE2012-21
Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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In this paper, we report a Global-Shutter CMOS Image Sensor with no picture distortion which caused due to line-scanned exposure. The midpoint potential drive technique enables the signal adaptive separation to MEM and FD, respectively. These signals are readout by using same Single-Slope ADC(SS-ADC) with operation range adjustment technique. The additional ADC circuit area is enough small to maintain the SS-ADC advantages. The enhanced dynamic range of 83.0dB is achieved by appropriate signal processing without influence of kT/C noise.
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Shinsaku HIURA
Article type: Article
Session ID: IST2012-10/CE2012-22
Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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The optical image on a sensor formed by a conventional lens mostly determines the quality of final image. Computational Photography is a concept to change the game of taking photograph by offering attractive functions such as blur reduction or posterior focus adjustment. In this framework, optical device is assumed as an encoder of sampled incoming rays, and the final image is reconstructed by decoding of the captured intensity distribution on the sensor. In this article I will introduce several basic concepts and achievements in this field by reproducing my talk in ISSCC2012.
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Yusuke TAKAHASHI, Yasufumi HIRAKAWA, Ryoma OAMI
Article type: Article
Session ID: IST2012-11/CE2012-23
Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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We propose a method considering privacy protection to extract visual features from surveillance video for human identification. This method extracts privacy-protected visual features on a small computer aside with a camera, and, instead of frames themselves, it sends only the irreversible visual features necessary for executing human identification on a server. While it takes more than 1000 ms for performing all the processes on the small computer, the proposed method can achieve it in less than 450 ms (more than 2fps) keeping privacy protected by appropriately separating the processes on the small computer and the server.
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Xinghua Hu, Makoto Ikeda
Article type: Article
Session ID: IST2012-12/CE2012-24
Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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Aiming at lack of clear evaluation methods for background light suppression characteristics and range finding accuracy towards smart image sensors for 3-D measurement using light section method, based on the analysis of typical smart image sensors for light section 3-D measurement, clear evaluation methods for background light suppression characteristics and range finding accuracy towards smart image sensors for 3-D measurement using light section method are presented, and some key questions are studied. The research results can provide evaluation methods for background light suppression characteristics and range finding accuracy of light section 3-D measurement using smart image sensors in the future.
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Toshihisa WATABE, Kazuya KITAMURA, Takehide SAWAMOTO, Tomohiko KOSUGI, ...
Article type: Article
Session ID: IST2012-13/CE-2012-2
Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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A 33-Mpixel 120-fps CIS with 12-bit column-parallel 2-stage cyclic ADCs and 96 parallel LVDS output ports which have a total data rate of 51.2 Gbps was fabricated. It exhibits ADC noise of 148.5μV_<rms>, and random noise of 5.8 e- at 120 fps, while dissipating 2.32 W. Increasing the analog gain up to 6.8 achieves low random noise of 3.7 e- while maintaining power consumption level of 2.54 W.
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Hisashi Watanabe, Jun Hirai, Motonari Katsuno, Keishi Tachikawa, Masao ...
Article type: Article
Session ID: IST2012-14/CE2012-26
Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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A frontside illuminated image (FSI) sensor with novel light guiding structures consisting of stacked lightpipes was developed using 45nm Cu processing on 300 mm wafers. We demonstrated a high quantum efficiency (QE) of 75% and maximum incident angle of 40°, which exceeds the performance of backside illuminated image (BSI) sensors [1,2,3].
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K. Itonaga, K. Mizuta, T. Kataoka, H. Ikeda, M. Yanagita, H. Ishiwata, ...
Article type: Article
Session ID: IST2012-15/CE2012-27
Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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We have developed a flat device structure, which we call "FLAT", with no isolation grooves/ridges and no Si substrate etching in the imaging area of the CMOS Image Sensor (CIS). We employed this FLAT structure to achieve a 1.12 μm pitch pixel CIS with a 1.25 transistor/pixel architecture and excellent image quality. It uses FLAT transistors (Trs) that generate greatly-reduced 1/f noise, and FLAT isolators (Isos) that increase the saturation capacity (Qs) due to increasing both effective photodiode (PD) area and PD potential under low dark current.
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Article type: Appendix
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Published: March 23, 2012
Released on J-STAGE: September 21, 2017
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Article type: Appendix
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Published: March 23, 2012
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Article type: Appendix
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Published: March 23, 2012
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