Journal of The Japan Institute of Electronics Packaging

Volume 1, Issue 5

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Intention to Special Issue for Trend of BGA·CSP·KGD

Kuniaki TAKAHASHI

1998 Volume 1 Issue 5 Pages 345
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.345

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Chip Size/Scale Package Mounting Technology for Personal Digital Assistants and Communication Tools

Seiji YAMAGUCHI

1998 Volume 1 Issue 5 Pages 346-350
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.346

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Chip Size/Scale Package Fabrication by Flip Chip Bonding Using Anisotropic Conductive Films

Tsuneo HAMAGUCHI

1998 Volume 1 Issue 5 Pages 351-355
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.351

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Evaluation Methods of CSP Mountability and Reliability

Hiroyuki HOSONO, Katsuya KOSUGA, Yoshikuni TANIGUCHI

1998 Volume 1 Issue 5 Pages 356-363
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.356

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Packaging Technology and Evaluation of Test Method Regarding BGA·CSP for Notebook PCs

Kuniaki TAKAHASHI, Hideki OGAWA

1998 Volume 1 Issue 5 Pages 364-370
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.364

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3-Dimensional Memory Module Using CSP

Yuzo SHIMADA

1998 Volume 1 Issue 5 Pages 371-375
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.371

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The Reliability of CSP/BGA Packaging Based on Simulation

Masazumi AMAGAI

1998 Volume 1 Issue 5 Pages 376-380
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.376

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Board Assembly Technology and Reliability of D²BGA CSP

Nobuki HIRAYAMA

1998 Volume 1 Issue 5 Pages 381-386
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.381

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The Reliability for μBGA^®

Yoshiro NISHIYAMA

1998 Volume 1 Issue 5 Pages 387-391
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.387

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Tape Type CSP and Its Material Technology

Osamu YOSHIOKA, Akira CHINDA

1998 Volume 1 Issue 5 Pages 392-397
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.392

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Flip-Chip Chip Size/Scale Package

Tadashi TAKAI

1998 Volume 1 Issue 5 Pages 398-400
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.398

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BGA, CSP and COB Based on Plastic Rigid PC Board

Yoshio IINUMA, Yoshihiro ISHIDA

1998 Volume 1 Issue 5 Pages 401-405
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.401

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Developing Trend of High Pin Count BGA

Morihiko IKEMIZU, Katsuto KATO

1998 Volume 1 Issue 5 Pages 406-409
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.406

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High Density BGA Substrates Fabricated by Laser Technologies

Fumitaka SATO

1998 Volume 1 Issue 5 Pages 410-413
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.410

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Trend of Build up PCB for CSP Mother Board Application

Shogo MIZUMOTO

1998 Volume 1 Issue 5 Pages 414-418
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.414

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Requirement for Bardie Quality from the User's Viewpoints—The Aim and Activity of KGD/Baredie Packaging Task Force

Akihiro DOHYA

1998 Volume 1 Issue 5 Pages 419-422
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.419

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The Electroplated Wafer Bumping Technology-The Gold and Solder Bump Process

Hiroshi MANITA

1998 Volume 1 Issue 5 Pages 423-428
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.423

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A Wafer-Level Burm-in Technology

Yoshiro NAKATA, Shinichi OKI, Tomoyuki NAKAYAMA, Kenjiro HIWATASHI

1998 Volume 1 Issue 5 Pages 429-433
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.429

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Current Status and Issues of Bare Chip Burn-In Technology-Report on Panel Discussion

Toshio SUDO

1998 Volume 1 Issue 5 Pages 434-438
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.434

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[title in Japanese]

[in Japanese]

1998 Volume 1 Issue 5 Pages 439-441
Published: October 01, 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.439

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ERRATUM

1998 Volume 1 Issue 5 Pages 443
Published: 1998
Released on J-STAGE: March 18, 2010

DOIhttps://doi.org/10.5104/jiep.1.443

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