This paper deals with a product testing method on a parallel and distributed system that consists of several test data acquisition devices and several test data processing devices. The test data acquisition device depicts data in a constant period and the data are sent to the test data processing device. In this system, acquisition and transmission of the test data takes several tens of milliseconds, and test data processing requires about a hundred milliseconds. In this environment, every test data acquisition must be assigned to a data processing device without blocking the next acquisition, while balancing the load among processors. This paper describes and discusses a testing system and a load balancing method. This system and the suggested method were evaluated against actual testing problems. As a result, the processing time was reduced by 72% and the required amount of memory was reduced by 99.7%, compared to a sequential process in which a certain number of data processing devices are available. Moreover, processing time and required amount of memory were reduced by 19% and 98.8%, respectively, compared with a random load balancing method.

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The three-dimensional (3D) chip stacking LSI under development in ASET uses new SIP (systemin-a-package) packaging technologies to realize high-density and high-speed transmission. Superfine flip-chip bonding utilizing micro bumps on Cu through-chip via (TCV) with a 20-μm-pitch is an important technology for realizing vertical interconnection, and ultrasonic flip chip bonding (UFB), utilizing Au bumps to connect the Cu TCV, is expected to enable a low-temperature and high-throughput process. In a basic study of the 20-μm-pitch Au bump interconnection, a thermo-compression bonding process was evaluated on a chip-on-chip (COC) structure. First, the mechanism of Au-Au thermo compression bonding with a recrystallization phenomenon across the bonding interface was confirmed. Second, it was confirmed that in the case of COC interconnections, the plastic strain range of the interconnections during temperature cycling tests (TCT) was mainly determined by the thermal mismatch in the thickness direction between the Au bump and the underfill resin. Finally, we developed a finite element method (FEM) analysis that corresponds well with the TCT results on the assumption that Au bump interconnection was composed of inhomogeneous crystal structure.

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[in Japanese]

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This study focused on the Au Au junction, using a sub-micron gold particle with low temperature sintering. The mechanical properties and the micro-structures were measured with the microbumps of the Au sintered compact, and mechanical shear fatigue tests for flip-chip specimens were then carried out. The cluster structure of the sintered bump heated at 220°C possessed ductility and turned to a grain growth structure with thermo-compression, resulting in a densely packed structure. In the mechanical shear fatigue test for the flip-chip specimens, the number of cycles to failure for the sintered bump was superior to that of a Sn-Ag alloy solder.

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