We have proposed a brand new model for semiconductor manufacturing system seamlessly integrating a wafer process-line with a packaging line. In the model, the following four features are introduced: a wafer package for a half-inch (ϕ 12.5 mm) wafer size, a mutual machine-size of 30 cm-width for every process, a clean-localized system for the whole manufacturing processes and, a flexible system that is responsible for a need of chip packaging started from one chip. To implement the model proposed, we have been developing a half-inch wafer packaging with a BGA (Ball Grid Array)-type solder array which consists of following processes: a compression molding, a laser via, a copper redistribution layer (RDL) patterning, a solder-ball mounting, and a reflow. All the newly developed machines for the processes above are employed to demonstrate a half-inch wafer in package. Some issues on patterning Cu electrical connection on top of the epoxy mold is focused and discussed in this work.

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SnO whisker with a tube-like shape was found on Sn plating or on Sn-Ag-Cu solder after humidity testing (85 ℃ 85 %RH). The SnO whisker is an insulator and it has no risk of short circuit fault. However, the formation of SnO whisker may have risk of corrosion. The growth mechanism of the tube-like SnO whisker was investigated. The tube-like SnO whisker is formed by bromination of Sn plating or Sn-Ag-Cu solder and oxidation of the surface of tin bromide in 85 ℃ 85 %RH atmosphere. Br included in flux residues causes bromination of Sn plating and organic acid included in flux residues casues the insulation deterioration of the flux residues.

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The paper reports about fabrication process, characterizations and transmission properties of screen printed transmission lines for on-wafer measurement at microwave and mm-wave frequencies. Firstly, fabrication process was optimized to achieve lower transmission loss at mm-wave frequency up to 110 GHz. Despite screen printed transmission lines had some defects such as voids and unideal cross sections, the transmission lines exhibited good transmission properties reached to those of conventional pleated technologies. Impedance Standard Substrate (ISS) was fabricated with printing technique and its calibration capability was compared to that of conventional ISS with a precision on-wafer measurement system. Although the developed printed ISS exhibited almost close calibration capability to conventional ISS, the differences were found in measured values of partial devices, which were caused by the defects of printed transmission lines.

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Curing behavior in air of epoxy-based electrically conductive adhesives composed of several types of amine-based curing agents containing copper micro-fillers was examined. Electrical conductivity was developed in these adhesives during gelation stage of the curing process. Electrical resistivity of the cured-adhesives varied depending on the amine-based curing agents. When a polyamide amine was used as the curing agent, relatively low electrical resistivity was obtained after curing. Although necking between copper fillers occurred in the epoxy-based binder during curing above 200 ℃, oxidation behavior of the fillers was quite different depending on the curing agents. Control of the interfacial reaction between copper fillers and chemical components of the binder is a key for development of air-curable adhesives containing copper fillers.

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The paper reports about fabrication process, characterizations and transmission properties of screen printed transmission lines Large area joining between a substrate and a heat sink is desirable for high performance power modules. We found that intermetallic compound (IMC) pillar dispersed solder is highly durable joint to achieve large area joining. The aim of this study is to clarify the mechanism of the strength reinforcement by IMC pillars. The structural characteristic of the solder joint was examined by cross-sectional observation, and the durability characterization was examined by FEM analysis. IMC pillars restrained cracks by obstructing crack propagation in the solder layer.

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Recently, Power devices have gotten a lot of attention in order to achieve low power consumption and downsizing for electrical equipment. Under such conditions, power packages are strongly required to have high heat dissipation structure with low on-state resistance and low inductance to decrease low power loss and high-speed switching noise. Panel Level Package (PLPTM) gives advantages on productivity, reliability and high-speed transmission characteristics. In this paper, we observed temperature rise at a line and vias during applying current of over 100 A to understand their design in PLPTM. We also simulated temperature distribution of the same model to research thermal behavior and compared with observed result.

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