MOSFET is a key component for integrated circuits which controls and helps the human activities in modern society. The demands for high performance and low power MOSFETs become stronger and stronger with the progress of smart society. Gate stack is the most critical element of the MOSFETs which controls its operation. In this report, after the explanation of the overall basics of the gate stack technology, recent status of the gate stack R & D are reviewed, focusing on that for high-k/metal gate stack.
We fabricate ultra-thin HfO2 gate stacks of very high permittivity value by using atomic layer deposition (ALD) and Ti-cap post deposition annealing. The HfO2 layer is directly deposited on hydrophilicized Si surface by ALD. A cubic crystallographic phase is generated in ALD-HfO2 by short time annealing with Ti capping layer. The Ti layer absorbs residual oxygen in HfO2 layer. The reduced oxygen concentration during annealing suppresses the growth of the interfacial SiO2 layer. The dielectric constant of ALD-HfO2 is enhanced to ～40, and extremely scaled ～0.2 nm equivalent oxide thickness of total gate stack is obtained.
In this work, we demonstrate high-performance silicon tri-gate nanowire transistor (NW Tr.) with NW width less than 15 nm. We successfully reduced the parasitic resistance of NW Tr. by raised source/drain extensions with thin spacers with < 10 nm. Furthermore, we introduced stress memorization technique (SMT) to NW Tr. And much larger mobility increase is obtained in NW Tr. than in planar Tr. The threshold voltage variability of NW Tr. is studied and the threshold voltage variability in NW Tr. is reduced compared to planar SOI Tr. due to gate grain alignment. The performance of NW Tr. CMOS circuits under the low voltage operation is investigated by using the Spice model parameters extracted from the measurement data. The operation voltage of NW CMOS inverter is reduced smaller than that of bulk CMOS due to the ideal sub-threshold slope. NW Tr. is highly promising for the ultra-low power and high-performance LSI applications.
This paper discusses the GeO2/Ge gate stack formation on the basis of the interface reaction control of Ge. The Ge oxidation is quite different from the Si one in terms of the fact that GeO desorption should be taken into account in the oxidation process. By using high-pressure oxidation, GeO desorption is thermodynamically suppressed, resulting that nearly perfect C-V characteristics in MOS capacitors and the record high electron mobility in n-channel MOSFETs have been demonstrated.
InGaAs MOS gate stack formation and the MOS interface control technologies, which are mandatory for realizing high performance InGaAs MOSFETs, are addressed with an emphasis on our recent achievements. Al2O3/InGaAs MOS gate stacks formed by Atomic Layer Deposition (ALD) are known as one of the most superior InGaAs MOS interfaces. The experimental results of Al2O3/InGaAs, HfO2/InGaAs and HfO2/Al2O3/InGaAs interfaces are presented. It is found that 1-nm-capaciatance equivalent thickness can be realized by HfO2/Al2O3/InGaAs gate stacks. Also, semiconductor inteface buffer layers inserted between InGaAs channels and gate oxides are shown to be effective in further improving the channel mobility.
Diamond is a new semiconductor which has been developed in the last around 15 years. It has unique properties and the potential of unique electronic devices. The typical example is negative electron affinity (NEA) for hydrogen terminated diamond surface. The nature of diamond electron affinity was investigated using by photo-yield spectroscopy (TPYS). Using the NEA property, electron emission p-n (p-i-n) diodes were fabricated, and this diode can be used as a new principle power device; a vacuum micro switch operated by a p-n diode.
Fundamental aspects of SiC oxidation and SiO2/SiC interfaces have been investigated to gain knowledge for improving performance and reliability of SiC-based MOS devices. High-resolution synchrotron x-ray photoelectron spectroscopy analysis revealed that a near-perfect interface dominated by Si-O bonds is formed by thermal oxidation of 4H-SiC(0001) substrates, but atomic scale roughness and imperfection causing electrical degradation of SiC-MOS devices are introduced as oxide thickness increases. We have also pointed out that the negative fixed charges originating from the interface defects modulate band offset at SiO2/SiC interface and that small conduction band offset leading toincreased gate leakage of MOS devices is an intrinsic problem, especially for the SiC(000-1) C-face substrates. On the basis of the results from the physical and electrical characterizations, this paper discusses the advantage of deposited insulating films on thin SiO2 underlayers in order to overcome these obstacles.