Significant advances in LSI interconnect technologies over the past two decades are overviewed especially for comparing Cu/Low-κ interconnects with previous Al interconnects. Cu damascene processes, Low-κ dielectric and barrier metal materials, and typical reliability failures such as the electro-migration (EM), the stress-migration (SM) and the time-dependent dielectric breakdown (TDDB) are described as key concerns about the miniaturization of Cu/Low-κ interconnects.
Cu(Mn) alloy seed BEOL studies revealed fundamental insights into Mn segregation and EM enhancement. A metallic-state Mn-rich Cu layer was under the MnOx layer at the Cu/SiCNH cap interface, and was correlated this metallic layer with additional EM enhancement. A carbonyl-based CVD-Co liner film consumed Mn, reducing its segregation and EM benefit, suggesting O-free Co liner films are strategic for Cu-alloy seed extendibility.
The present work investigated the behavior of resistivity increase in Cu interconnects utilizing Monte Carlo simulation. We developed efficient Monte Carlo method to estimate the size effect on resistivity in nanoscale interconnects structure. In the dimension where line width and film thickness becomes a dimension comparable to the electron mean free path, the multiple interface scattering occurred around the corners of interconnects and it became a dominant factor for the resistivity increase. In terms of interface scattering, controlling Line Edge Roughness (LER) and Line Width Roughness (LWR) is important to suppress the resistivity increase. It is preferable that LER wavelength is longer than electron mean free path and subsequently LWR is minimalized. In terms of grain boundary scattering, enhancing the average grain size is an effective method to suppress the resistivity increase.
The contributions of the “interface” on interconnect reliability are investigated in some previous work. For electromigration and stress-induced voiding, Cu/dielectrics interface has a key role as a dominant diffusion path of Cu. A surface treatment after chemical mechanical polishing affects lifetime distribution of time-dependent dielectric breakdown. The defect density on the interface is a key factor to control the early failure. In this paper, some advanced metallization process and its effects to suppress the reliability issues are introduced. To adapt the novel process technologies successfully in product line, these results will provide valuable information.
Cu-Cu direct bonding is one of key issues in 3D integration. Although there are several methods for Cu bonding such as thermo compression bonding and Cu-Sn liquid-solid inter-diffusion bonding, reduction of the high bonding temperature and removal of the oxide on Cu surface are still central challenges. The surface activated bonding (SAB) provides a unique method to bond different kinds of materials at room temperature, based on the concept of the nature of solids surfaces that chemical bonds are generated spontaneously by contact of atomically clean and activate surfaces. The present paper describes the current status of the low temperature bonding techniques for 3D integration is reviewed. Especially the SAB method is focused and explored in terms of its feasibility in applications on Cu-Cu direct bonding for TSV stack.