This tutorial focuses on designing a mechanism that achieves a socially desirable outcome or a goal of the designer that arises from some practical demands, as several advanced topics on mechanism design theory. We first briefly explains the theory of combinatorial auctions via the most well-known Vickrey-Clarke-Groves mechanism. Second, as an example that designs a new mechanism for a practical demand, we introduce false-name bids and illustrate how we improve a trivial robust mechanism against false-name bids. Furthermore, we explore models and several theoretical results on mechanisms of a keyword auction and a two-sided matching as other well-known topics of mechanism design theory.
In software development projects, document artifacts have an important role as a form of communication. As a result, many documents are prepared and updated frequently in a large software system development project. In such a situation, it is difficult to analyze and review many documents manually. Recently, there are many researches for analyzing document artifacts by applying technologies such as document structure analysis, string analysis and natural language processing. In this paper, we review the works on document artifact analyisis technologies and their applications.
Research area of eating and cooking activities include sharing, analysis, helping about cooking, health assistance of eating, analysis of communication about eating with other people and measuring and outputting information of taste. Among them, various technologies of outputting about information of taste are proposed. In this thesis, we surveyed outputting information of taste utilizing information technology and computer science. We classified these output system of taste information according type of direct output to our sensor organ and indirectness output. In addition, we discussed about the wave of the future of these system and research and contribution of these methodology for eating and cooking activities.
Due to available of large FPGAs, FPGAs are used for implementing not only simple hardware logics, but also complicated algorithms. By the reason, FPGAs are pointed out as execution platforms of program. Although RLT design is widely used for development hardware logic on FPGA, the RTL design for a complicated algorithm is an inconvenient and time-consuming approach. Therefore, high-level synthesis languages (HLSLs) are desired to design hardware in a higher abstraction level than RTL. HLSLs are needed to ease hardware design, to decrease verification, and to exploit the performance of the FPGA. This paper surveys HLSLs and high-level synthesizers.
In this paper, we present a survey of automatic music generation systems from the viewpoint of creative process framework. According to Shneiderman's framework, a creative process consists of four phases: Collect, Relate, Create, and Donate. Regarding a system, a user, and a system designer as a total system, we investigate which of them achieves each of the four phases and how in existing music generation systems, especially music composition, arrangement, and performance rendering systems. Our investigation shows common and different parts in the four phases among the systems, which implied a direction to future music generation studies.
For ensuring safety of an embedded system, it is required to demonstrate that the system has sufficient safety measures to mitigate hazardous failures identified by safety analysis. Developers of safety-critical embedded systems need a guideline and criterion to appropriately choice safety measures for products certification based on international functional safety standards. Although many safety measures for software faults have been researched, definitions of terminology and its taxonomy have not been established because each measure has been developed separately. Based on the automotive functional safety standard ISO 26262, this paper presents a guideline for safety design and choice of safety measures for software faults, and taxonomy of safety mechanisms.
Expectations for and interests in making strategic use of large-scale dataset called big data have been increasing in recent years. This paper provides a comprehensive review of studies on basic software technologies for storing and parallel processing big data. We also try to give a big picture of big data technologies and discuss technical and social trends in the future.
In this paper, we present an interval tense logic with the inclusion modality, together with the precedence modality. We show that our interval tense logics are decidable. We also investigate the fundamental features of logic to represent realistic temporal intervals, and among them we propose the notion of embeddability of a frame into the time axis, by which all the intervals are mapped into the time axis. Although the class of embeddable frames is not modally definable, we show a decision procedure whether given finite frames are embeddable.
Roundtrip engineering is an approach where models and source code are refined by iteratively conducting forward and reverse engineering. It enables more efficient development of software, e.g. through reducing development time, and is especially said to be effective for applications that have frequent changes in requirements, such as Web applications. Imazeki, et al., have proposed an approach for realizing roundtrip engineering for Web applications. However, current roundtrip engineering approaches and tools cannot handle Ajax applications. The main reason for this is the main characteristic of Ajax, which is the asynchronous processing between clients and server. We propose an approach that realizes roundtrip engineering for Ajax applications. Our approach is implemented on top of a roundtrip engineering tool for Web applications proposed by Imazeki. We show a case study as well as an experimental result to show the effectiveness of our tool. The experimental result showed that our tool was able to reduce the time to conduct a maintenance task by 25%.
This paper presents how to build a type debugger without reimplementing a type inference engine. Previous type debuggers required their own type inference engines apart from the compiler's built-in engine. The advantage of our approach is threefold. First, by not reimplementing it, it is guaranteed that the debugger's type inference never disagree with the compiler's type inference. Secondly, we can avoid the pointless reproduction of a type inference engine that should work precisely as the compiler's type inference engine. Such a reproduction would be a cumbersome and error-prone task for a full-fledged language. Thirdly, our approach is robust to updates of the underlying language. In this article, we will describe how our technique is applied to the simply-typed lambda calculus and let-polymorphism, and report on the prototype type debugger for OCaml.
Commutativity is a generalization of confluence. Furthermore, decompositions of term rewriting systems based on the commutativity is useful to prove confluence of term rewriting systems. Several methods for showing commutativity of term rewriting systems are known, where all of them are based on conditions imposed from critical pairs analysis. Apart from this, a sufficient condition of commutativity based on decreasing diagrams has been studied in the framework of abstract rewriting. Decreasing diagrams, however, have not been applied for proving commutativity of term rewriting systems. In this paper, we introduce one side decreasing diagrams, and give a method to prove commutativity of term rewriting systems based on one side decreasing diagrams.
We propose a modeling method used in design space exploration of architectures of embedded systems. Modeling cost for performance evaluation tends to be too high for an architect to evaluate many architecture alternatives. Our method exploits a UML-based model transformation from an architecture expression to a simulation model to reduce the cost. A case study reveals that our method reduces the cost by more than a factor of 1/3 from that of manual modeling.
This paper proposes a new SAT encoding method, named compact order encoding, which encodes arithmetic constraints used in Constraint Satisfaction Problems on finite integer domains. The basic idea of the compact order encoding is the use of a numeral system of some base B ≥ 2 to represent integer variables, and each digit of variables is encoded by using the order encoding. It is equivalent the log encoding when B = 2, and it is equivalent to the order encoding when B is larger than the domain size of integer variables. Therefore, it can be seen as a generalization of the log and order encodings. We confirmed that the compact order encoding is applicable to wide range of problems from small-scale (where domain size of variables is less than 102) to large-scale (where domain size of variables is about 107), and shows better performance than log encoding, order encoding, and existing constraint solvers through experimental comparisons on Open- Shop Scheduling and Graph Coloring which are typical constraint satisfaction problems. From those results, although further comprehensive experiments will be necessary for selecting base B, it can be said that the compact order encoding is one of the effective SAT encodings at the current moment applicable to wide range of problems in various scales.
We designed and implemented a Lisp environment called LESA for interactive development of distributed applications. LESA is based on Safe Ambients, a process algebra that has the notion of locations called ambients. By introducing ambients, LESA makes it easy to construct distributed applications hierarchically and view their structures. Furthermore, we enhanced the interactive environment of Lisp to fit the computation model of Safe Ambients. Using this, for instance, multiple users can develop distributed applications cooperatively by connecting their environments with each other. Users can also develop applications progressively and interactively by representing their functions as processes and then adding them into the initial ambient (home ambient) in a series of small steps. Moreover, LESA has GUI that displays the hierarchical structure of the whole ambient at runtime.
August 28, 2017 There had been a service stop from Aug 28‚ 2017‚ 1:50 to Aug 28‚ 2017‚ 10:08(JST) (Aug 27‚ 2017‚ 16:50 to Aug 28‚ 2017‚ 1:08(UTC)) . The service has been back to normal.We apologize for any inconvenience this may cause you.
July 31, 2017 Due to the end of the Yahoo!JAPAN OpenID service, My J-STAGE will end the support of the following sign-in services with OpenID on August 26, 2017: -Sign-in with Yahoo!JAPAN ID -Sign-in with livedoor ID * After that, please sign-in with My J-STAGE ID.
July 03, 2017 There had been a service stop from Jul 2‚ 2017‚ 8:06 to Jul 2‚ 2017‚ 19:12(JST) (Jul 1‚ 2017‚ 23:06 to Jul 2‚ 2017‚ 10:12(UTC)) . The service has been back to normal.We apologize for any inconvenience this may cause you.
May 18, 2016 We have released “J-STAGE BETA site”.
May 01, 2015 Please note the "spoofing mail" that pretends to be J-STAGE.