Computer Software

The Internet

Hideki SUNAHARA

2014 Volume 31 Issue 4 Pages 4_1
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_1

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Introduction to the Special Issue on Software Papers

Seiji UMATANI, Yasuyuki KONO, Tsuneyasu KOMIYA, Katsuhiko GONDOW, Hiro ...

2014 Volume 31 Issue 4 Pages 4_2
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_2

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GKJ: Groupware for Paper-based KJ Labelwork

Motoki MIURA

2014 Volume 31 Issue 4 Pages 4_3-4_8
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_3

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Cat Knows Quantum Programming

Kentaro HONDA, Yoshihiko KAKUTANI, Takahiro KUBOTA

2014 Volume 31 Issue 4 Pages 4_9-4_20
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_9

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A Report on CHI 2014: The ACM CHI Conference on Human Factors in Computing Systems 2014

Takuro KURIBARA

2014 Volume 31 Issue 4 Pages 4_21-4_25
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_21

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Report on ACM MobiSys 2014

Yoshito TOBE

2014 Volume 31 Issue 4 Pages 4_26-4_29
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_26

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Report on PLDI 2014 and ISMM 2014

Tomoharu UGAWA

2014 Volume 31 Issue 4 Pages 4_30-4_35
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_30

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Report of FM2014

Fuyuki ISHIKAWA

2014 Volume 31 Issue 4 Pages 4_36-4_39
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_36

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Design Verification by Model Checking

Nobukazu YOSHIOKA, Yoshinori TANABE, Yasuyuki TAHARA, Tetsuo HASEGAWA, ...

2014 Volume 31 Issue 4 Pages 4_40-4_65
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_40

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As performance of devices become high and growing networks between the devices, parallel and distributed systems providing advanced features become popular. It is hard to verify the behavior of such systems' design with traditional techniques, such as manual reviews and simulations, because of so many possibilities of the behavior. Model Checking is the one of promising techniques to tackle the difficulty. In this paper, we introduce the background of Model Checking techniques and show five popular model checking tools with the case studies and current research topics.

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Variability Modeling Methods for Software Product Line Development

Natsuko NODA, Tomoji KISHI

2014 Volume 31 Issue 4 Pages 4_66-4_76
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_66

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In software product-line development (SPLD), variability management plays an essential role, and multiple variability modeling methods have been proposed. Along with gradual acceptance of SPLD and diversifications of the usage of variability models, there have been proposed various enhancements on these models. In this tutorial paper, we focus on feature model, a representative variability model. We firstly introduce the original feature model and some extensions made on the model, and then introduce how these models are used in SPLD activities.

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Improving the Real-time Performance of a General-purpose OS through Timer Shielding

Masahiro YAMADA, Yoshitake KOBAYASHI, Shinya HONDA, Hiroaki TAKADA

2014 Volume 31 Issue 4 Pages 4_77-4_96
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_77

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With the increase in hardware performance of modern embedded systems, general-purpose operating systems (OS) such as Linux are commonly used as embedded OSs. Furthermore, the use of multi-core CPUs enables Linux to improve its real-time performance even on high-load scenarios which is rather hard to achieve on single-core CPUs thanks to its “CPU affinity” functionality. However, we found two issues in the current version of the Linux kernel: the CPU affinity of some kernel threads cannot be specified; and the use of timer cascading (use of multiple hardware timers to count time) increases the worst-case response time of real-time tasks. In this paper, we classify the cores in a multi-core CPU into 2 different groups: cores which require real-time performance guarantees; and cores which do not require such guarantees. Then, we propose and evaluate a method that improves the real-time performance of the system by disabling timer cascading on cores which require real-time performance guarantees.

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To browse or to search, is that the question?

Shingo TAKADA

2014 Volume 31 Issue 4 Pages 4_98-4_99
Published: October 24, 2014
Released on J-STAGE: December 24, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_98

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Software Component Technology for Embedded Systems with Memory Protection

Takuya ISHIKAWA, Takuya AZUMI, Hiroshi OYAMA, Shinya HONDA, Hiroaki TA ...

2014 Volume 31 Issue 4 Pages 4_105-4_130
Published: October 24, 2014
Released on J-STAGE: November 28, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_105

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This paper describes HR-TECS which is a new component technology for embedded software that requires memory protection, which is one of the important features for the software partitioning. HR-TECS is based on TECS which is a component technology for embedded software, and takes advantage of functionalities of a real-time operating system with memory protection. In addition, interfaces for communications between components do not depend on partitions which the components are allocated to. Thus, components can be implemented without consideration for the component partitioning. Furthermore, not only components which are executed in a user mode (e.g. application software) but also components which are executed in a privileged mode (e.g. device drivers) can be developed with HR-TECS. This paper presents the way to implement HR-TECS by taking advantage of TOPPERS/HRP2 kernel which is a real-time operating system with memory protection. The results of evaluation demonstrate the effectiveness of HR-TECS that its execution time is sufficiently small and predictable, and its memory consumption is sufficiently small.

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A Weighted Type-Error Slicer

Kanae TSUSHIMA, Kenichi ASAI

2014 Volume 31 Issue 4 Pages 4_131-4_148
Published: October 24, 2014
Released on J-STAGE: November 28, 2014

DOIhttps://doi.org/10.11309/jssst.31.4_131

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This paper presents how to construct a weighted type-error slice without reimplementing a type inference engine. In the previous type-error slices, we had no information on the source of the type error in the slices. However, we encounter many examples where the possibility that the source of a type error in a slice is not uniform. In this work, we present a weighted type-error slicer. We provide information on how often each part of a slice contribute to type conflicts. The advantage of our approach is twofold. First, we use compiler's type inference engine to make type-error slices. By not reimplementing it, we can obtain scalability and maintainability. Second, we have weights on type-error slices. We can use the information to improve the behavior of type debuggers. In this paper, we introduce an embedded type-error slicer. After that, we extend it to introduce weights.

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