An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the effective data capacity, and for an optimal exploitation of this capacity for given power dissipation. At high level, this asks for a new view on the so-called client-server relations in the chain. To substantiate this vision, some examples of research projects in our group are addressed. These include FE-driven transmission schemes, duty-cycled operation with wake-up radio, programmable FEs, smart antenna-FE combinations, smart and flexible converters, and smart pre and post correction.

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This paper describes recent technology trend of mixed analog digital RF circuits. With the progress of CMOS technology, large-scale digital signal process and control function can be integrated in an RF integrated circuit and some analog signal process blocks can be translated to digital signal processing units. At the same time, the design of remaining analog functional blocks becomes very hard. In this paper, those integration techniques for receiver and transmitter in these 20 years are reviewed. As a typical example of digital assisted systems, synthesizer based transmitters are discussed in detail.

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A novel DC-to-960MHz impulse radio ultra-wideband (IR-UWB) transceiver based on threshold detection technique is developed. It features a digital pulse-shaping transmitter, a DC power-free pulse discriminator and an error-recovery phase-frequency detector. The developed transceiver in 90nm CMOS achieves the lowest energy consumption of 2.2pJ/bit transmitter and 1.9pJ/bit receiver at 100Mbps in the UWB transceivers.

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Frequency dependent properties of accumulation-mode MOS varactors, which are key elements in many RF circuits, are dominated by Non-Quasi-Static (NQS) effects in the carrier transport. The circuit performances containing MOS varactors can hardly be reproduced without considering the NQS effect in MOS-varactor models. For the LC-VCO circuit as an example it is verified that frequency-tuning range and oscillation amplitude can be overestimated by over 20% and more than a factor 2, respectively, without inclusion of the NQS effect.

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A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63GHz and consumes 78mW from a 1.2V supply. The phase noise at 100kHz and 1MHz offset from carrier are -72 and -80dBc/Hz, respectively. The prescaler occupies 80 × 40µm². The active area of the PLL is 0.31mm².

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A decoupling device that can be used for millimeter-waves is required to reduce the effect of the parasitic impedance at the grounded terminal of the power supply. The frequently used decoupling capacitor is not appropriate because it has self-resonance characteristics due to the parasitic inductance. To realize resonance-free wideband decoupling, a high-attenuation power line (HAPL) is proposed. The HAPL has constant input impedance equal to its characteristic impedance, and has constant isolation unaffected by the phase constant and the terminal impedance. Furthermore, the HAPL contributes to the area reduction of the millimeter-wave circuits because it simultaneously acts as a power line and a decoupling device. The HAPL was fabricated with a 90nm CMOS process. The proposed structure increases parallel conductance and capacitance using an MOS capacitor and its equivalent series resistance, therefore realizing high attenuation and resonance suppression while reducing characteristic impedance. With a 200-µm-long HAPL, Re (S11) was less than -0.9 and isolation was more than 25dB, from 50GHz to 90GHz including unlicensed bands used for wireless personal area network and radar application. As a result, power-supply network with wideband decoupling is realized by simply connecting power-supply pads and feeding point via the HAPL. The HAPL is expected to contribute to the simple and compact design of millimeter-wave circuits.

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This paper presents a multi functional range finder employing dual imager core on a single chip. Each imager core has functionalities of 2-D imaging and 3-D capture using the light section method with combinations of the dual imager core. The presented chip achieves, 2-D imaging mode, 3-D capture mode with the conventional light-section method, high-speed 3-D capture mode with the stereo matching mode, and 2-D and 3-D simultaneous capture mode. We demonstrate 58fps 2-D imaging with 8 bit gray scale, and 24.8 rangemaps/s 3-D range-finder with the maximum range error of 1.619mm and the standard deviation of 0.385mm at 700mm.

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Analog multipliers are one of the most important building blocks in analog signal processing circuits. The performance with high linearity and wide input range is usually required for analog four-quadrant multipliers in most applications. Therefore, a highly linear and wide input range four-quadrant CMOS analog multiplier using active feedback is proposed in this paper. Firstly, a novel configuration of four-quadrant multiplier cell is presented. Its input dynamic range and linearity are improved significantly by adding two resistors compared with the conventional structure. Then based on the proposed multiplier cell configuration, a four-quadrant CMOS analog multiplier with active feedback technique is implemented by two operational amplifiers. Because of both the proposed multiplier cell and active feedback technique, the proposed multiplier achieves a much wider input range with higher linearity than conventional structures. The proposed multiplier was fabricated by a 0.6µm CMOS process. Experimental results show that the input range of the proposed multiplier can be up to 5.6V_pp with 0.159% linearity error on VX and 4.8V_pp with 0.51% linearity error on VY for ±2.5V power supply voltages, respectively.

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In this paper we propose a novel functional amplifier suitable for low-power wireless receivers in a wireless sensor network. This amplifier can change input threshold level as carrier sensing level, since it has a minimum input amplitude to be amplified. A simple rail-to-rail output is suitable for a subsequent digital interface. The target frequency is 433MHz, and the maximum voltage gain is 11dB. The standby power is 39.5nW, and the active power is 352µW. The chip area is 82 × 24µm².

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This paper presents a 1V operating fully differential OTA using NMOS inverters in place of the traditional differential pair. To obtain high gain, a two-stage configuration is used in which the first stage has feedforward paths to cancel the common-mode signal, and the second stage has common-mode feedback paths to stabilize the output common-mode voltage. The proposed OTA was fabricated by an 0.18µm CMOS technology. Measured gain is 40dB and GBW is 10MHz, in addition to differential output voltage swing of 1.8V_p-p. It is confirmed that the proposed OTA can operate from 1V power supply and has very large output swing capability even in a 1V operation. The proposed OTA configuration contributes to a solution to the low power supply voltage issue in scaled CMOS analog circuits.

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Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90nm CMOS technology. A 2Vpp input voltage range and 50µW power consumption were achieved by the measurements with a 0.5V supply. High accuracy of 62dB SNR was obtained at signal bandwidth of 120kHz.

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A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057MHz, respectively, at 32M samples/s. The converter consumes 0.89mA and 0.42mA in the analog and digital component, respectively, at a 1.8-V supply.

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Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15pJ/conversion-step.

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Time-interleaving is an efficient approach to increase the effective sampling rate of the ΣΔ modulators, but time-interleaved (TI) ΣΔ modulators are sensitive to channel mismatch, which causes the quantization noise folded back into the band of interest. To reduce the folded noise caused by the channel mismatch of two-channel TI ΣΔ modulators, a low-power second-order two-channel TI ΣΔ modulator is proposed. The noise transfer function (NTF) of the modulator is a band-pass filter. By using this band-pass NTF, the folded noised can be reduced. The entire modulator can be implemented by employing three op-amps, which is beneficial for power consumption. The circuit of implementation for the proposed modulator is designed in 0.18µm COMS technology. The proposed modulator can achieve a SNDR of 78.9dB with a channel mismatch of 0.5% and a linear gradient mismatch of 0.4% for unity sampling capacitors. Monte Carlo simulation is done with a random Gaussian mismatch of 0.4% standard deviation for all capacitors, resulting in an average SNDR of 80.5dB. It is indicated that the proposed TI modulator is insensitive to the channel mismatch. The total power consumption is 19.5mW from a 1.8V supply.

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This paper presents a system architecture for sensor signal digitization utilizing a band-pass sigma-delta modulator (BP ΣΔM). The first version of the proposed system architecture was implemented in 5V 0.7µm CMOS technology. The proposed system architecture is useful for our capacitive pressure sensor measurement. The paper describes the possibilities of using the proposed enhanced system architecture in impedance spectroscopy and in capacitive pressure sensor measurement. The BP ΣΔM is well suited for wireless applications. This paper shows another way how to use its advantages.

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A wide range, low jitter Duty Cycle Corrector (DCC) based on continuous-time integrator is proposed. It introduces little added jitter in the sampling edge, which make it good candidate for pipelined ADC application. The circuit is implemented in CMOS 0.35µm 2P4M Mixed Signal process. The experimental results show the circuit can work for a wide frequency range from 500kHz to 280MHz, with a correction error within 50%±1% under 200MHz, and the acceptable duty cycle can be as wide as 1-99% for low frequency inputs.

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This paper presents a high-throughput bit-serial low-density parity-check (LDPC) decoder that uses an asynchronous interleaver. Since consecutive log-likelihood message values on the interleaver are similar, node computations are continuously performed by using the most recently arrived messages without significantly affecting bit-error rate (BER) performance. In the asynchronous interleaver, each message's arrival rate is based on the delay due to the wire length, so that the decoding throughput is not restricted by the worst-case latency, which results in a higher average rate of computation. Moreover, the use of a multiple-valued data representation makes it possible to multiplex control signals and data from mutual nodes, thus minimizing the number of handshaking steps in the asynchronous interleaver and eliminating the clock signal entirely. As a result, the decoding throughput becomes 1.3 times faster than that of a bit-serial synchronous decoder under a 90nm CMOS technology, at a comparable BER.

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Negative bias temperature instability (NBTI) has become a critical reliability phenomena in advanced CMOS technology. In this paper, we propose an analytical temperature-aware dynamic NBTI model, which can be used in two circuit operation cases: executing tasks with different temperatures, and switching between active and standby mode. A PMOS V_th degradation model and a digital circuits' temporal performance degradation estimation method are developed based on our NBTI model. The simulation results show that: 1) the execution of a low temperature task can decrease ΔV_th due to NBTI by 24.5%; 2) switching to standby mode can decrease ΔV_th by 52.3%; 3) for ISCAS85 benchmark circuits, the delay degradation can decrease significantly if the circuit execute low temperature task or switch to standby mode; 4) we have also observed the execution time's ratio of different tasks and the ratio of active to standby time both have a considerable impact on NBTI effect.

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The polarization dependence of the resonance wavelength of long period fiber gratings (LPFGs) that employ the photoelastic effect is investigated based on a simple model. The proposed model for estimating the birefringence of these LPFGs provides a good explanation of the experimental results.

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A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600MHz and 8.35µW at a 0.5V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.

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A high-sensitivity pickup tube using HARP (high-gain avalanche rushing amorphous photoconductor) photoconductive film, which makes use of the avalanche multiplication phenomenon, has been studied for making a high-sensitivity television camera. The avalanche multiplication factor, i.e., sensitivity, was increased by thickening the film. A 35-µm-thick HARP film, which was more sensitive than the previous 25-µm-thick film with an avalanche multiplication factor of about 600, and a 2/3rd-inch pickup tube using the film were developed. Measurements on the pickup tube demonstrated that it had an avalanche multiplication factor of about 1000, low lag, and high resolution. Moreover, image defects caused by shooting of intense spot lights were investigated, and it was found that exposing the film to UV light before operation and controlling the temperature of the film during operation could suppress the defects.

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The vacuum sealing process with a base vacuum of 10^-5 Torr is adopted to minimize the residual impurity gas. The address and sustain discharges in the 42-in PDP prepared by the vacuum-sealing process are observed by using the ICCD. As a result, the ICCD observation illustrates that thanks to the reduction of the impurity level by the vacuum-sealing process, the surface and plate-gap discharges are initiated and extinguished very fast and the corresponding IR emissions are also intensified.

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