Effects of stress in passivation films on the electrical properties of (0001) AlGaN/GaN HEMTs are numerically analysed in the framework of the edge force model with anisotropical characteristics in elastic properties of group-III nitrides explicitly considered. Practical compressive stresses in passivation films induce negative piezoelectric charges below the gates and bring forth a-few-volt shallower threshold voltages. In addition, the shift in the threshold voltage due to the compressive stress is proportional to L _G^-1.1∼-1.5 with gate length L _G, which is comparable to the expectation based on the charge balance scheme. These result suggest that passivation films with designed stress might play a crucial role in realising AlGaN/GaN HEMTs with shallow or positive threshold voltages.

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Drain collapse in AlGaN/GaN HFET is analyzed using a two-dimensional device simulator. Two-step saturation is obtained, assuming hole-trap type surface states on the AlGaN surface and a short negative-charge-injected region at the drain side of the gate. Due to the surface electric potential pinning by the surface traps, the negative charge injected region forms a constant potential like in a metal gate region and it acts as an FET with a virtual gate. The electron concentration profile reveals that the first saturation occurs by pinch-off in the virtual gate region and the second saturation occurs by the pinch-off in the metal gate region. Due to the short-channel effect of the virtual gate FET, the saturation current increases until it finally reaches the saturation current of the intrinsic metal gate FET. Current collapses with current degradation at the knee voltage in the I-V characteristics can be explained by the formation of the virtual gate.

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The large signal performance and model for GaN FET devices was evaluated with DC, S-parameters, and large signal measurements. The large signal model was extended with bias and temperature dependence of access resistances, modified capacitance and charge equations, as well as breakdown models. The model was implemented in a commercial CAD tool and exhibits good overall accuracy.

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To improve the high voltage performance of AlGaN/GaN heterojunction field effect transistors (HFETs), we have fabricated AlGaN/GaN HFETs with p-GaN epi-layer on sapphire substrate with an ohmic contact to the p-GaN (p-sub HFET). Substrate bias dependent threshold voltage variation (V_T-V_SUB) was used to directly determine the doping concentration profile in the buffer layer. This V_T-V_SUB method was developed from Si MOSFET. For HFETs, the insulator is formed by epitaxially grown and heterogeneous semiconductor layer while for Si MOSFETs the insulator is amorphous SiO₂. Except that HFETs have higher channel mobility due to the epitaxial insulator/semiconductor interface, HFETs and Si MOSFETs are basically the same in the respect of device physics. Based on these considerations, the feasibility of this V_T-V_SUB method for AlGaN/GaN HFETs was discussed. In the end, the buffer layer doping concentration was measured to be 2 × 10¹⁷cm^-3, p-type, which is well consistent with the Mg concentration obtained from secondary ion mass spectroscopy (SIMS) measurement.

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This work addresses the enormous efficiency and linearity potential of optimized AlGaN/GaN high-electron mobility transistors (HEMT) in conventional Doherty linear base-station amplifiers at 2.7GHz. Supported by physical device simulation, the work further elaborates on the use of AlGaN/GaN HEMTs in high-speed current-switch-mode class-D (CMCD)/class-S MMICs for data rates of up to 8Gbit/s equivalent to 2GHz RF-operation. The device needs for switch-mode operation are derived and verified by MMIC results in class-S and class-D operation. To the authors' knowledge, this is the first time 2GHz-equivalent digital-switch-mode RF-operation is demonstrated with GaN HEMTs with high efficiency.

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The paper presents a systematic study of in-situ passivated AlN/GaN Metal Insulator Semiconductor Field Effect Transistors (MISFETs) with submicron gates. DC, high frequency small signal, large signal and low frequency dispersion effects are reported. The DC characteristics are analyzed in conjunction with the power performance of the device at high frequencies. Studies of the low frequency characteristics are presented and the results are compared with those of AlGaN/GaN High Electron Mobility Transistors (HEMTs). Small signal measurements showed a current gain cutoff frequency and maximum oscillation frequency of 49.9GHz and 102.3GHz respectively. The overall characteristics of the device include a peak current density of 335mA/mm, peak extrinsic transconductance of 130mS/mm, a maximum output power density of 533mW/mm with peak power added efficiency (P.A.E.) of 41.3% and linear gain of 17dB. The maximum frequency dispersion of transconductance and output resistance of the fabricated MISFETs is 20% and 21% respectively.

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E-band low-noise amplifier (LNA) monolithic millimeter-wave integrated circuits (MMICs) were developed using pseudomorphic In_0.75Ga_0.25As/In_0.52Al_0.48As high electron mobility transistors (HEMTs) with a gate length of 50nm. The nanogate HEMTs demonstrated a maximum oscillation frequency (ƒ_max) of 550GHz and a current-gain cutoff frequency (ƒ_T) of 450GHz at room temperature, which is first experimental demonstration that ƒ_max as high as 550GHz are achievable with the improved one-step-recessed gate procedure. Furthermore, using a three-stage LNA-MMIC with 50-nm-gate InGaAs/InAlAs HEMTs, we achieved a minimum noise figure of 2.3dB with an associated gain of 20.6dB at 79GHz.

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We theoretically study the performance limits of current-gain cutoff frequency, ƒ_T, for the HEMTs with InAs or In_0.70Ga_0.30As middle layers in the multi-quantum-well (MQW) channels by means of the quantum-corrected Monte Carlo (MC) method. We calculate the distribution of the delay time along the channel, τ(x), and define the effective gate length, L_{g, eff}, as the corresponding length to (x). By extrapolating L_{g, eff} to L_g = 0nm, we estimate the lower limit of L_{g, eff}, L_{g, eff}⁽⁰⁾. Then we estimate the performance limit of ƒ_T, ƒ_T⁽⁰⁾, by extrapolating ƒ_T to L_{g, eff}⁽⁰⁾. The estimated ƒ_T⁽⁰⁾ are about 3.6 and 3.7THz for the HEMTs with InAs middle layers of 5 and 8nm in thickness, and about 3.0THz for the HEMT with In_0.70Ga_0.30As middle layer of 8nm in thickness, respectively. The higher ƒ_T⁽⁰⁾ in the HEMTs with InAs middle layers are attributed to the increased average electron velocity, v_d, in the channel. These results indicate the superior potential of the HEMTs using InAs in the channels. The HEMT with InAs middle layer of 8nm in thickness shows the highest ƒ_T on condition of the same L_g because of its highest v_d. However, the increased total channel thickness results in the longer L_{g, eff}⁽⁰⁾, which leads to the restriction of ƒ_T⁽⁰⁾. Therefore, in order to increase ƒ_T⁽⁰⁾, it is essential to make L_{g, eff} short in addition to making v_d high. Our results strongly encourage in making an effort to develop the HEMTs that operate in the terahertz region.

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A monolithic modulator driver IC based on InP HBTs with a new circuit topology — called a functional distributed circuit (FDC) — for over 80-Gb/s optical transmission systems has been developed. The FDC topology includes a wide-band amplifier designed using a distributed circuit, a digital function designed using a lumped circuit, and broadband impedance matching between the lumped circuit and distributed circuit to enable both wider bandwidth and digital functions. The driver IC integrated with a 2: 1 multiplexing function produces 2.6-V_p-p (differential output: 5.2V_p-p) and 2.4-V_p-p (differential output: 4.8V_p-p) output-voltage swings with less than 450-fs and 530-fs rms jitter at 80Gb/s and 90Gb/s, respectively. To the best of our knowledge, this is equivalent to the highest data rate operation yet reported for monolithic modulator drivers. When it was mounted in a module, the driver IC successfully achieved electro-optical modulation using a dual-drive LiNbO₃ Mach-Zehnder modulator up to 90Gb/s. These results indicate that the FDC has the potential to realize high-speed and functional ICs for over-80-Gb/s transmission systems.

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We fabricated a 2: 1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120Gbit/s with a power dissipation of 1.27W and output amplitude of 520mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4W.

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This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ƒ_t of 175GHz and a peak ƒ_max of 260GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/−0.07 LSB and +0.27/−0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7dB for a sinusoidal output of 72.5MHz at a sampling rate of 13.5GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24GS/s are also obtained. The total power consumption is as low as 0.88W with a supply voltage of −4.0V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5bits or more.

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We report on the first terahertz emission from a novel dual grating gate plasmon-resonant emitter fabricated with InAlAs/InGaAs/InP material systems. The introduction of InP based heterostructure material systems, instead of the GaAs based ones, in order to improve the quality factor, has successfully enhanced the THz emission intensity and realized the spectral narrowing at room temperature.

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A third order harmonic oscillator has been proposed based on the resonant tunneling diode pair oscillators. This oscillator has significant advantages, good stability of the oscillation frequency against the load impedance change together with capability to output higher frequencies. Proper circuit operation has been demonstrated using circuit simulations. It has been also shown that the output frequency is stable against the load impedance change.

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We derive physics-based formula of current-voltage characteristic for resonant tunneling diodes (RTDs) by using the Voigt function. The Voigt function describes the mixing condition of homogeneous and inhomogeneous broadenings of peak energy width in transmission probability, which is sensitively reflected to nonlinear negative differential resistance of RTDs. The obtained formula is applicable to the SPICE model of RTD without performing numerical integrals. We indicate validity of the formula by comparing to measured data for double-barrier and triple-barrier RTDs.

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Novel thermopiles based on modulation doped AlGaAs/InGaAs, AlGaN/GaN, and ZnMgO/ZnO heterostructures are proposed and designed for the first time, for uncooled infrared image sensor application. These devices are expected to offer high performances due to both the superior Seebeck coefficient and the excellently high mobility of 2DEG and 2DHG due to high purity channel layers at the heterojunction interface. The AlGaAs/InGaAs thermopile has the figure-of-merit Z of as large as 1.1 × 10^-2/K (ZT = 3.3 over unity at T = 300K), and can be realized with a high responsivity R of 15, 200V/W and a high detectivity D^∗ of 1.8 × 10⁹cmHz^1/2/W with uncooled low-cost potentiality. The AlGaN/GaN and the ZnMgO/ZnO thermopiles have the advantages of high sheet carrier concentration due to their large polarization charge effects (spontaneous and piezo polarization charges) as well as of a high Seebeck coefficient due to their strong phonon-drag effect. The high speed response time τ of 0.9ms with AlGaN/GaN, and also the lower cost with ZnMgO/ZnO thermopiles can be realized. The modulation-doped heterostructure thermopiles presented here are expected to be used for uncooled infrared image sensor applications, and for monolithic integrations with other photon detectors such as InGaAs, GaN, and ZnO PiN photodiodes, as well as HEMT functional integrated circuit devices.

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A unipolar n-n heterostrucuture diode is developed in the InP material system. The electronic barrier is formed by a saw tooth type of conduction band bending which consists of a quaternary In_0.52(Al_yGa_1-y)_0.48As layer with 0 < y < y_max•. This barrier is lattice matched for all y to InP and is embedded between two n⁺-InGaAs layers. By varying the maximum Al-content from y_{max, 1} =0.7 to y_{max, 2} =1 a variable barrier height is formed which enables a diode-type I-V characteristic by epitaxial design with an adjustable current density within 3 orders of magnitude. The high current density of the diode with the lower barrier height (y_{max, 1} = 0.7) makes it suitable for high frequency applications at low signal levels. RF measurements reveal a speed index of 52ps/V at V_D = 0.15V. The device is investigated for RF-to-DC power conversion in UHF RFID transponders with low-amplitude RF signals.

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This paper presents a compact and highly integrated triple-band RF front-end module (FEM) for worldwide interoperability for microwave access (WiMAX) applications using multilayer low temperature co-fired ceramic (LTCC) technology. The proposed RF FEM is composed of a TX triplexer, an RX triplexer, and a TX/RX switch. Both TX and RX triplexers are fully embedded in an LTCC substrate and the TX/RX switch is placed on the substrate. The TX triplexer consists of 2- and 5-GHz lowpass filters, a 3-GHz highpass filter, and a matching circuit. On the other hand, the RX triplexer consists of miniaturized 2-, 3-, 5-GHz coupled-resonator bandpass filters and a matching circuit, which are stacked up for space saving. In TX path, the RF FEM provides an insertion loss of 1.8dB, 2.1dB and 2.5dB at 2-, 3-, and 5-GHz band, respectively, with a high second-harmonic suppression characteristic. In RX path, the RF FEM also provides a low insertion loss at three passbands with high attenuation at other passbands. The size of the proposed RF FEM is only 4.0mm × 5.0mm with a substrate thickness of 0.73mm. The measured results are in good agreement with the simulated results.

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A rectifying antenna is one of the most important components for wireless power transmission applications. In our previous papers, some RF-DC conversion circuits with high conversion efficiency at low input power are proposed. However, these RF-DC conversion circuits have some parts of which size depends on operating frequency, so the circuit size becomes large at low operating frequency. And, the composition of these RF-DC conversion circuits is complicated. Therefore, in this paper, a new RF-DC conversion circuit composed of only chip devices is proposed. This circuit has higher conversion efficiency than the previously proposed circuits. And, size reduction of the RF-DC conversion circuit is realized. Moreover, the composition of the circuit is simple, so the circuit size does not depend on operating frequency. For design of the RF-DC conversion circuits, LE-FDTD method is used. The measurement results agree with analytical results of the LE-FDTD method very well, and availability of the LE-FDTD method is discovered. It is shown that LE-FDTD method is a powerful analytical way which can give efficient design of RF-DC conversion circuit with high conversion efficiency.

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A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10µm and L = 0.18µm in a 16 × 16 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7mV and 32.2mV, respectively, for the temperature range from −25°C to 75°C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10mV/bit and 3.53mV/bit at 25°C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125ns, which corresponds to the 8-MHz throughput.

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This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.

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Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.

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In order to quickly discharge the electrostatic discharge (ESD) energy, an unassisted low-voltage-trigger ESD protection structure is proposed in this work. Under transmission line pulsing (TLP) stress, the trigger voltage, turn-on speed and second breakdown current can be obviously improved, as compared with the traditional protection structure. Moreover there is no need to add any extra mask or do any process modification for the new structure. The proposed structure has been verified in foundry's 0.18-µm CMOS process.

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We propose a low-power eFuse one-time programmable (OTP) memory IP based on a bipolar CMOS DMOS (BCD) process. It is an eFuse OTP memory cell which uses separate transistors that are optimized in program and in read mode. The eFuse cell also uses poly-silicon gates having co-silicide. An asynchronous interface and a separate I/O method are used for the low-power and small-area eFuse OTP memory IP. Additionally, we propose a new circuit protecting a short-circuit current in the VDD-to-VIO voltage level translator circuit while the VDD voltage is being generated by the voltage regulator at power-up. A digital sensing circuit using clocked inverters is used to sense a bit-line (BL) datum. Furthermore, the poly-silicon of the IP is split into n+ poly-silicon and p+ poly-silicon to optimize the eFuse link. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18µm BCD process is 283.565 × 524.180µm². It is measured by manufactured test IPs with Dongbu HiTek's 0.18µm BCD process that the programming voltage of the n+ gate poly-silicon is about 0.1V less than that of the p+ gate poly-silicon.

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We present an improved perfectly matched layer (PML) for the analysis of plasmonic structures, based on the manipulation of PML parameters. Two different types of stretched coordinate PML are employed sequentially in the spatial domain: a real stretched coordinate PML to increase the effective buffer space around plasmonic structures and a complex stretched coordinate PML to absorb outgoing waves and terminate the computational domain. Numerical examples show that a significant increase in computational efficiency is obtained because the proposed PML can be placed closer to plasmonic structures than the regular PML without affecting the field distribution of bound modes.

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A low-voltage class-AB CMOS output stage with a tunable quiescent current control circuit is presented. It is based on a complementary common source. The quiescent current is detected by a compact circuit and can be adjusted by means of a control current without need to modify the transistor dimensions. The minimum supply voltage can be down to one threshold voltage plus two saturation voltages. It is suitable to drive low resistive loads. Simulation results are provided that are in agreement with expected characteristics.

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