Progress of roles and schemes of calibration techniques in data converters are reviewed. Correction techniques of matching error and nonlinearity in analog circuits have been developed by digital assist using high-density and low-power digital circuits. The roles of the calibration are not only to improve accuracy but also to reduce power dissipation and chip area. Among various calibration schemes, the background calibration has significant advantages to achieve robustness to fast ambient change. Firstly the nonlinearity calibrations for pipeline ADCs are reviewed. They have required new solutions for redundancy of the circuits, an error estimation algorithm and reference signals. Currently utilizing the calibration techniques, the performance of 100Msps and 12bit has been achieved with 10mW power dissipation. Secondly the background calibrations of matching error in flash ADC and DAC with error feedback to the analog circuits are described. The flash ADC utilizes the comparator offset correction with successive approximation algorithm. The DAC adopts a self current matching scheme with an analog memory. Measured dissipation power of the ADC is 0.38mW at 300MHz clock. Effects of the background calibration to suppress crosstalk noise are also discussed.

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Digital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRP^TM) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and built-in self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as ‘soft specifications’, are defined.

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In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

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This paper describes a new technique for the design of 3-terminal regulators in which the output voltage level can be adjusted without additional terminals or extra off-chip components. This circuit restricts the increase in the number of terminal pins by using a pin as both a voltage supply output and a voltage setup input. The voltage setup information is introduced using a serial control signal from outside the chip. Using the intermediate voltage level between the supply voltage and the regulator output, the adjustment data in the internal nonvolatile memory are safely updated without noise disturbance. To input the setup information into the chip in a stable manner, we developed a new 1-wire serial interface which combines key pattern matching and burst signal detection. To ensure high reliability, we suggested a quantitative method for evaluating the influence of noise in our new interface using a simple model with superimposed random noise. Circuits additional to those for a conventional 3-terminal regulator, include a 1-wire serial communication circuit, a low-capacity non-volatile memory, and a digital to analog (D/A) converter. A test chip was developed using 0.35µm standard CMOS process, and there was almost no overhead to the conventional 3-terminal regulator in both chip area and power dissipation. In an on-board test with the test chip, we confirmed successful output voltage adjustment from 1.0V to 2.7V with approximately 6.5mV precision.

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In this paper, a novel switched-capacitor DC-DC converter with pulse density and width modulation (PDWM) is proposed with reduced output ripple at variable output voltages. While performing pulse density modulation (PDM), the proposed PDWM modulates the pulse width at the same time to reduce the output ripple with high power efficiency. The prototype chip was implemented using 65nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional PDM scheme, the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.

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This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18µm CMOS process, and simulation results are presented. With a 1.6V supply, the reference produces an output of about 628.5mV, and simulated results show that the temperature coefficient of output is less than 13.8ppm/°C in the temperature range from 0°C to 100°C. The average current consumption is about 8.5µA in the above temperature range. The core circuit, including current source, opamp, current mirrors and switched capacitor filters, occupies less than 0.0064mm² (80µm × 80µm).

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An area efficiency hybrid decoupling scheme is proposed to suppress the charge pump noise during F-N tunneling program in non-volatile memory (NVM). The proposed scheme is focused on suppressing the average noise power in frequency domain aspect, which is more suitable for the program error reduction in NVMs. The concept of active capacitor is utilized. Feed forward effect of the amplifier is firstly considered in the impedance analysis, and a trade-off relation between in-band and out-band frequency noise decoupling performance is shown. A fast optimization based on average noise power is made to achieve minimum error in the F-N tunneling program. Simulation results show very stable output voltage in different load conditions, the average ripple voltage is 17mV with up to 20dB noise-suppression-ratio (NSR), and the F-N tunneling program error is less than 5mV for a 800µs program pulse. A test chip is also fabricated in 0.18µm technology. The area overhead of the proposed scheme is 2%. The measurement results show 24.4mV average ripple voltage compared to 72.3mV of the conventional one with the same decoupling capacitance size, while the noise power suppression achieves 15.4dB.

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A differential BPSK transmitter for ultra-wideband impulse-radio communication has been presented in this paper. The transmitter, developed in a 65nm CMOS process,is simple in design and occupies a core area of 0.0017mm². The differential Gaussian monocycle pulses (GMP) are generated using some logic blocks and delay elements. The generated GMP, having a center frequency above 5GHz, meets the FCC regulations. Measured results show that the transmitter consumes 1.8pJ/bit to transmit BPSK modulated GMP at a data rate of 2Gb/s. The interface circuitries eliminate the need for external networks for chip to antenna matching. Using an off-chip differential bow-tie antenna, data can easily be transmitted up to a distance of 10cm which made it suitable for low power far field non-coherent applications.

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A 0.6-V voltage shifter and a 0.6-V clocked comparator are presented for sampling correlation-based impulse radio UWB receiver. The voltage shifter is used for a novel split swing level scheme-based CMOS transmission gate which can reduce the power consumption by four times. Compared to the conventional voltage shifter, the proposed voltage shifter can reduce the required capacitance area by half and eliminate the non-overlapping complementary clock generator. The proposed 0.6-V clocked comparator can operate at 100-MHz clock with the voltage shifter. To reduce the power consumption of the conventional continuous-time comparator based synchronization control unit, a novel clocked-comparator based control unit is presented, thereby achieving the lowest energy consumption of 3.9pJ/bit in the correlation-based UWB receiver with the 0.5ns timing step for data synchronization.

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A capacitive coupling wireless connector circuit is implemented with 50µm × 50µm pads, which is a 25X reduction of pad size compared with previous wireless connectors by allowing contacting and non-contacting modes. The proposed track and charge scheme allows both contacting and non-contacting communication through PCB capacitive pads. By making the precharge level of the input V_DD or V_SS, instead of 1/2V_DD, the time necessary to precharge is reduced. The proposed digitally tunable comparator does not require analog voltages, reduces the power to less than 1/20 at lower frequencies compared to previous capacitive coupling receivers. A test chip successfully transmitted and received 1Gb/s, 2⁷-1PRBS signal at 1mW while increasing design freedom of the wireless connectors.

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Source-follower-based (SFB) continuous-time low-pass filters (LPF) have the advantages of low power and high linearity over other filter topologies. The second-order SFB filter cells, which are key building blocks for high-order SFB filters, are often realized by composite source follower with positive feedback. For a single branch 2nd-order SFB cell, the linearity drops severely at high frequencies in the pass band because its slew-rate is restricted by the Q factor and the pole frequency. The folded 2nd-order SFB cell provides higher linearity because it has two DC branches, and hence has another freedom to increase the slew rate. However, because of the positive feedback, the folded and unfolded 2nd-order SFB cells, especially those with high Q factors, tend to be unstable and act as relaxation oscillators under given circuit parameters. In order to obtain higher Q factor, a new topology for the 2nd-order SFB cell without positive feedback is proposed in this paper, which is unconditionally stable and can provide high linearity. Based on the folded 2nd-order SFB cell and the proposed high-Q SFB cell, a 264MHz sixth-order LPF with 3 stages for ultra wideband (UWB) applications is designed in 0.18µm CMOS technology. Simulation results show that the LPF achieves an IIP3 of above 12.5dBm in the whole pass band. The LPF consumes only 4.1mA from a 1.8V power supply, and has a layout area of 200µm × 150µm.

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In this paper we present eigenmode analysis of the propagation constant for a microstrip line with dummy fills on a Si CMOS substrate. The effect of dummy fills is not negligible, particularly in the millimeter-wave band, although it has been ignored below frequencies of a fewGHz. The propagation constant of a microstrip line with a periodic structure on a Si CMOS substrate is analyzed by eigenmode analysis for one period of the line. The calculated propagation constant and characteristic impedance were compared with measured values for a chip fabricated by the 0.18µm CMOS process. The agreement between the analysis and measurement was very good. The dependence of loss on the arrangement of dummy fills was also investigated by eigenmode analysis. It was found that the transmission loss becomes large when dummy fills are arranged at places where the electromagnetic field is strong.

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A diagnosis testbench of analog IP cores characterizes their coupling strengths against on-chip environmental disturbances, specifically with regard to substrate voltage variations. The testbench incorporates multi-tone digital noise generators and a precision waveform capture with multiple probing channels. A prototype test bench fabricated in a 90-nm CMOS technology demonstrates the diagnosis of substrate coupling up to 400MHz with dynamic range of more than 60dB. The coefficients of noise propagation as well as noise coupling on a silicon substrate are quantitatively derived for analog IP cores processed in a target technology, and further linked with noise awared EDA tooling for the successful adoption of such IP cores in SoC integration.

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A single tone pseudo-noise generator with a harmonic-eliminated waveform is proposed for measuring noise tolerance of analog IPs. In the waveform, the harmonics up to the thirteenth are eliminated by combining seven rectangular waves with 22.5- degree spacing phases. The proposed waveform includes only high region frequency harmonic components, which are easily suppressed by a low-order filter. This characteristic enables simple circuit implementation for a sine wave generator. In the circuit, the harmonic eliminated waveform generator is combined with a current controlled oscillator and a frequency adjustment circuit. The single tone pseudo-noise generator can generate power line noise from 20MHz to 220MHz with 1MHz steps. The SFDR of 40dB is obtained at the noise frequency of 100MHz. The circuit enables the measurement of frequency response characteristics measurements such as PSRR.

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In this paper, a differential input/output linear MOS transconductor using an adaptively biasing technique is proposed. The proposed transconductor based on a differential pair is linearized by employing an adaptively biasing circuit. The linear characteristic of the individual differential output currents are obtained by introducing the adaptively biased currents to terminate the differential output terminals. Using the proposed technique, the common-mode rejection ration (CMRR) becomes high. Simulation results show that the proposed technique is effective for improvement of the linearity and other performances.

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We propose a subthreshold Static Random Access Memory (SRAM) circuit architecture with improved write ability. Even though the circuits can achieve ultra-low power dissipation in subthreshold digital circuits, the performance is significantly degraded with threshold voltage variations due to the fabrication process and temperature. Because the write operation of SRAM is prone to failure due to the unbalance of threshold voltages between the nMOSFET and pMOSFET, stable operation cannot be ensured. To achieve robust write operation of SRAM, we developed a compensation technique by using an adaptive voltage scaling technique that uses an on-chip threshold voltage monitoring circuit. The monitoring circuit detects the threshold voltage of a MOSFET with the on-chip circuit configuration. By using the monitoring voltage as a supply voltage for SRAM cells, write operation can be compensated without degrading cell stability. Monte Carlo simulations demonstrated that the proposed SRAM architecture exhibits a smaller write operation failure rate and write time variation than a conventional 6T SRAM.

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A 60-GHz injection-locked frequency divider (ILFD) is presented. A multi-order LC oscillator topology is proposed to enhance the locking range of the divider. A design guideline is described based on a theoretical analysis of the locking range enhancement. A test chip is fabricated in 65nm CMOS. Measured locking range with 0dBm input power is 48.5-62.9GHz (25.9%), which is 63.6% wider compared to the previously reported ILFD. Power consumption excluding buffers and biasing circuits is 1.65mW from 1.2V supply. The core ILFD area is 0.0157mm² even with an extra pair of inductors.

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Conventional multi-gate pseudomorphic high-electron-mobility transistors (pHEMTs) in the off-state generate larger distortion than single-gate pHEMTs in RF switch applications. To reduce the distortion, the intergate region of multi-gate pHEMTs must be connected to the source and drain with resistors to be biased at the same DC voltage. The intergate region of multi-gate pHEMTs is too small to have an external electrical contact, so intergate-channel-connected pHEMTs (IGCC-pHEMTs) have been developed. IGCC-pHEMTs have a meander gate structure, where one side of the gate is connected to a metal wire layer, and the other is applied for an intergate region contact that does not widen the distance between the gates. A single-pole double-throw (SPDT) switch with IGCC-pHEMTs was fabricated by using a standard 0.5µm InGaAs pHEMT process. A SPDT switch with IGCC-pHEMTs is confirmed to have almost same small-signal properties and generate lower distortions.

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This paper presents measurement of on-chip coupling between PA and LNA integrated on Si CMOS substrate, which is caused by substrate coupling, magnetic coupling, power-line coupling, etc. These components are decomposed by measurements using diced chips. The result reveals that the substrate coupling is the most dominant in CMOS chips and the total isolation becomes less than -50dB with more than 0.4mm PA-to-LNA distance.

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This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

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Digital delta-sigma modulators (DDSMs) applied in fractional-N frequency synthesizers suffer from spurious tones which undermine the synthesizer's spectral purity. We propose a solution featuring no hardware overhead while achieving equivalent spur elimination effect as using LFSR-dithering. This method can be implemented on MASH and single-loop DDSMs of 3rd- and 2nd-order.

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A bootstrapped analog switch with constant on-resistance is proposed for the successive approximation (SA) analog-to-digital converters (ADCs) that have many input-sampling switches. The initialization circuit, which is composed of a short pulse generator and a transmission gate, improves the linearity of the proposed bootstrapped analog switch by reducing the effect of the capacitive load. To evaluate the proposed bootstrapped analog switch, the 10-bit 1MS/s CMOS SA ADC with a rail-to-rail differential input signal was designed by using a 0.18µm CMOS process with 1.0V supply voltage. The proposed bootstrapped analog switch reduced the maximum V_GS variation of the conventional bootstrapped analog switch by 67%. It also enhanced the signal to noise-distortion ratio of the SA ADC by 4.8dB when the capacitance of its gate node is 100fF, and this improvement was maximized when the capacitance of its gate node increases.

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Dependence of within-die delay variations on power supply voltage (V_DD) is measured down to 0.4V. The V_DD dependence of the within-die delay variation of manual layout and irregular auto place and route (P&R) layout are compared for the first time. The measured relative delay (=sigma/average) variation difference between the manual layout and the P&R layout decreases from 1.56% to 0.07% with reducing V_DD from 1.2V to 0.4V, because the random delay variations due to the random transistor variations dominate total delay variations instead of the delay variations due to interconnect length variations at low V_DD.

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This paper presents an accurate and systematic method to simulate the interference imposed on the input/output (I/O) ports of electronic equipment under the electrical fast transients/burst (EFT/B) test. The equivalent circuit of the EFT/B generator and the coupling clamp are modeled respectively. Firstly, a transfer function (TF) of the EFT pulse-forming network is constructed with the latent parameters based on circuit theory. In the TF, two negative real parameters characterize the non-oscillation process of the network while one complex conjugate pair characterizes the damping-oscillation process. The TF of the pulse-forming network is therefore synthesized in the equivalent circuit of the EFT/B generator. Secondly, the standard coupling clamp is modeled based on the scatter (S) parameter obtained by using a vector network analyzer. By applying the vector fitting method during the rational function approximation, a macromodel of the coupling clamp can be obtained and converted to a Spice compatible equivalent circuit. Based on the aforementioned procedures, the interference imposed on the I/O ports can be simulated. The modeling methods are validated experimentally, where the interference in differential mode and common mode is evaluated respectively.

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A micro-power active-RFID LSI with an all-digital RF-transmitting scheme achieves experimental 10-m-distance communication with a 1-Mbps data rate in the 300-MHz frequency band. The IC consists of an RF transmitter and a power supply circuit. The RF transmitter generates wireless signals without a crystal. The power supply circuit controls the energy flow from the battery to the IC and offers intermittent operation of the RF transmitter. The IC draws 1.6µA from a 3.4-V supply and is implemented in a 0.2-µm CMOS process in an area of 1mm². The estimated lifetime of the IC is over ten years with a coin-size battery.

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This paper develops planar circuit filters consisting of arbitrarily-shaped conductor patches and slots on a conductor-backed dielectric substrate, which are designed by an optimization technique based on the genetic algorithm. The developed filter has multiple resonators and their mutual couplings in the limited space by using both sides of the substrate, so that its compactness is realized. We first demonstrate the effectiveness of the present filter structure from some design samples numerically and experimentally. Then as a practical application, we design compact UWB filters, and their filter characteristics are verified from the measurements.

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This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier (TDA) and shows measurement results with 0.18µm CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on a lookup table. The wide input range mode shows 10.2ps time resolution over 1.3ns input range with DNL and INL of +0.8/-0.7LSB and +0.8/-0.4LSB, respectively. The fine time resolution mode shows 1.0ps time resolution over 60ps input range with DNL and INL of +0.9/-0.9LSB and +0.8/-1.0LSB, respectively.

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This paper introduces the ensemble Monte Carlo (EMC) method to study the time behavior of single-electron-based logic gates. The method is then applied to a buffer-inverter gate and the results are examined. An analytical model for time behavior at the low-temperature limit is then introduced and its results are compared with those of the EMC. Finally, a compact model for the delay-error behavior of the buffer gate is introduced.

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This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 32×32, two 16×16 or four 8×8 signed multiply-accumulation. Experimentally, when implemented with a 130nm CMOS single-V_t standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-V_t standard cell library.

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The asymmetrical halo and dual-material gate structure is used in the surrounding-gate metal-oxide-semiconductor field effect transistor (MOSFET) to improve the performance. By treating the device as three surrounding-gate MOSFETs connected in series and maintaining current continuity, a comprehensive drain current model is developed for it. The model incorporates not only channel length modulation and impact ionization effects, but also the influence of doping concentration and vertical electric field distributions. It is concluded that the device exhibits increased current drivability and improved hot carrier reliability. The derived analytical model is verified with numerical simulation.

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This paper presents the design of a wideband low noise amplifier (LNA) for the 3GPP LTE (3rd Generation Partnership Project Long Term Evolution) standard. The proposed LNA uses a common gate topology with a noise cancellation technique for wideband (0.7 to 2.7GHz) and low noise operation. The capacitive cross coupling technique is adopted for the common gate amplifier. Consequently input matching is achieved with lower transconductance, thereby reducing the power consumption and noise contribution. The LNA is designed in a 0.18µm process and the simulations show lower than -10dB input return loss (S11), and 2.4∼2.6dB noise figure (NF) over the entire operating band (0.7∼2.7GHz) while drawing 9mA from a 1.8V supply.

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Clocked cascade voltage switch logic (C²VSL) circuits with gated feedback were newly designed for synchronous systems. In order to investigate single event transient (SET) effects on the C²VSL circuits, SET effects on C²VSL EX-OR circuits were analyzed using SPICE. Simulation results have indicated that the C²VSL have increased tolerance to SET.

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We proposed and analyzed a fiber-reinforced ceramic (FRC) composite for a protection layer on top of an antenna mounted on the outer surface of aircraft. The manufactured FRC is a single-layered flat construct. To analyze the performance of the FRC, we extracted the material constant using the transmission/reflection (T/R) method. We described the relation between the pressure and strength of the FRC radome with respect to mechanical properties and analyzed the insertion loss with respect to electrical properties. We evaluated the characteristics of the FRC radome in conjunction with the horn antenna and showed that the analytic results for the FRC radome agree with the experiment results.

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This paper proposes a technique for two-stage operational amplifiers (OPAMPs) to optimize power consumption according to various channel conditions of wireless communication systems. The proposed OPAMP has the ability of reducing the quiescent current of each stage independently by introducing additional common-mode feedback, therefore more optimization is possible according to the channel conditions than conventional two-stage OPAMPs. The simulations verify the benefits of the technique. As a proof-of-concept topology, the proposed OPAMPs were used in a channel-selection filter for a multi-standard mobile-TV receiver. The power consumption of the filter, 3.4-5.0mW, was adjustable according to the bandwidth, the noise, and the jammer level. The performance of the filter meets the requirements and verifies the effectiveness of the proposed approach. The filter was fabricated in 0.18-µm CMOS and occupied 0.64mm².

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