Abstract The concept, state of the art, and future development directions of hybrid semiconductor integrated circuits (HySICs), which combine RF-CMOS ICs with compound semiconductor monolithic microwave integrated circuits (MMICs) are described in this paper, taking up recent wireless technologies as example applications. It is shown that ICs with superior function can be designed by mixing the optimal characteristics from the different semiconductors. To realize new semiconductor ICs, several component technologies for RF-HySIC are introduced in terms of chip/MMIC design, measurement, and breadboard model fabrication. A prototype RF-HySIC is described for the combination of a GaN Schottky barrier diode with a Si RF-IC matching network developed at 5.8GHz. A GaN diode structure, measurement and characterization of nonlinear devices, a GaN amplifier, and a GaAs MMIC are introduced as component technologies. In addition, the design for using an RF-CMOS matching network circuit with a size of 1.2mm × 2.3mm and room-temperature chip/wafer direct bonding under high-pressure conditions are explained. For advanced and autonomous ICs, HySIC and chip/MMIC topologies combined with a processor are proposed for application of HySIC to wireless sensor systems.

This paper presents an innovative fabrication process for a planar circuits at millimeter-wave frequency. Screen printing technology provides low cost and high performance coplanar waveguides (CPW) lines in planar devices operated at millimeter-wave frequency up to 110GHz. Printed transmission lines provide low insertion losses of 0.30dB/mm at 110GHz and small return loss like as impedance standard lines. In the paper, Multiline Thru-Reflect-Line (TRL) calibration was also demonstrated by using the impedance standard substrates (ISS) fabricated by screen printing. Regarding calibration capability validation, verification devices were measured and compare the results to the result obtained by the TRL calibration using commercial ISS. The comparison results obtained by calibration of screen printing ISS are almost the same as results measured based on conventional ISS technology.

The most commonly used scattering parameters (S parameters) are normalized to a real reference resistance, typically 50Ω. In some cases, the use of S parameters normalized to some complex reference impedance is essential or convenient. But there are different definitions of complex-referenced S parameters that are incompatible with each other and serve different purposes. To make matters worse, different simulators implement different ones and which ones are implemented is rarely properly documented. What are possible scenarios in which using the right one matters? This tutorial-style paper is meant as an informal and not overly technical exposition of some such confusing aspects of S parameters, for those who have a basic familiarity with the ordinary, real-referenced S parameters.

Design of lumped-element immittance inverters which support dual-frequency operation and tuning of both operational frequencies is presented. Unique properties of the dual-composite right/left-handed transmission lines (D-CRLH TL) give an opportunity to design immittance inverters with two non-multiple operational frequencies and a stop band between them. Replacement of capacitors of D-CRLH TL unit cells with variable ones enables inverter tunability. Tunability analysis of such immittance inverters is given. It is shown that a tuning range of the operational frequencies is limited by a tolerable variation of the inverter parameter. The design concept is verified by results of electromagnetic simulation and measured frequency characteristics of fixed (non-tunable) as well as tunable dual-frequency immittance inverters and dual-band filters using the inverters.

This paper proposes a new and simple microstrip bandpass filter structure for the design of a fully canonical transversal array filter. The filter is constructed by the parallel arrangement of microstrip even- and odd-mode half-wavelength resonators. In this filter, transmission zeros (TZs) are not produced by cross couplings used in conventional filter designs, but by an intrinsic negative coupling of the odd-mode resonators having open ends with respect to the even-mode resonators with shorted ends. Thus, the control of the resonant frequency and the external Q factor of each resonator makes it possible to form both a specified passband and TZs. As an example, a fully canonical bandpass filter with 2-GHz center frequency, 6% bandwidth, and four TZs is synthesized with a coupling-matrix optimization, and its structural parameters are designed. The designed filter achieves a rapid roll-off and low-loss passband response, which can be confirmed numerically and experimentally.

A broadband miniature GaAs p-HEMT MMIC Doherty power amplifier (DPA) with a series connected load operating at the C band has been developed. To minimize the circuit size, a lumped-element load modulation circuit without a quarter wavelength transmission line has been introduced to MMIC technology. For both an input and output power divider/combiner circuit, two baluns are used to reduce the length of the phase adjuster circuit without causing instability. An inherent DPA instability problem related with the degenerated sub-harmonic frequency has been analyzed with the S and T parameters of DPA circuit components, resulting in a novel stabilized circuit. The developed stabilized DPA delivered a maximum power added efficiency (PAE) of 49% and a maximum output power of 23.4dBm. Greater than 40% PAE below a 10-dB input back-off from a saturated output power is obtained for a frequency range of 6.1 to 6.8GHz.

The high performance GaN power amplifier circuit operating at 7.1 GHz was demonstrated for potential use such as in a space ground station. First, the GaN HEMT chips were investigated for the high power amplifier circuit design. And next, the designed amplifier circuits matching with the load and source impedance of the non-linear models were fabricated. From measurement, the AB-class power amplifier circuit with the four-cell chip showed the power added efficiency (PAE) of 42.6% and output power with 41.7dBm at -3dB gain compression. Finally, the good performance of the power amplifier was confirmed in a 20-way radial power combiner with the PAE of 17.4% and output power of 52.6 dBm at -3dB gain compression.

A novel experimental design method based on a low-frequency active load-pull technique that includes harmonic tuning has been proposed for high-efficiency microwave power amplifiers. The intrinsic core component of a transistor with a maximum oscillation frequency of more than several tens of gigahertz can be approximately assumed as the nonlinear current source with no frequency dependence at an operation frequency of several gigahertz. In addition, the reactive parasitic elements in a transistor can be omitted at a frequency of much less than 1GHz. Therefore, the optimum impedance condition including harmonics for obtaining high efficiency in a nonlinear current source can be directly investigated based on a low-frequency active harmonic load-pull technique in the low-frequency region. The optimum load condition at the operation frequency for an external load circuit can be estimated by considering the properties of the reactive parasitic elements and the nonlinear current source. For an InGaAs/GaAs pHEMT, active harmonic load-pull considering up to the fifth-order harmonic frequency was experimentally carried out at the fundamental frequency of 20MHz. By using the estimated optimum impedance condition for an equivalent nonlinear current source, high-frequency amplifiers were designed and fabricated at the 1.9-GHz, 2.45-GHz, and 5.8-GHz bands. The fabricated amplifiers exhibited maximum drain efficiency values of 79%, 80%, and 74% at 1.9GHz, 2.47GHz, and 5.78GHz, respectively.

This paper presents a wideband differential amplifier operating at 141GHz in 40-nm CMOS. It is composed of five differential common source stages with cross-coupled capacitors. A small-signal gain of 20dB and a 3-dB bandwidth of 22GHz are achieved. It consumes 75mW from a 0.94-V voltage supply. The die area with balun and pads is 945×842µm² and the size of the core not including input/output matching networks is 201×284µm². The small core area is made possible by using a refined “fishbone” layout technique.

This paper presents a modulation scheme for impulse radio that uses the first sidelobe for transmitting a non-return-to-zero baseband signal and the implementation of a dual frequency conversion demodulator. The proposed modulation technique realizes two times higher frequency efficiency than that realized by binary phase-shift keying modulation and does not require an up-converter in the transmitter. The dual frequency conversion demodulator compensates for the spectrum distortion caused by the frequency response of the circuits and channel. The effect of frequency compensation is analytically studied. The fabricated demodulator test chip of 65 nm CMOS achieves clock and data recovery at 5.7 Gbps with a power consumption of 24 mW.

Antenna radiation patterns have side-lobes that add to ambiguity in the form of ghosting and object repetition in SAR images. An L-band 1.27GHz, 2×5 element proximity-coupled corner-truncated patch array antenna synthesized using the Dolph-Chebyshev method to reduce side-lobe levels is proposed. The designed antenna was sim-ulated, optimized, and fabricated for antenna performance parameter measurements. Antenna performance characteristics show good agree-ment with simulated results. A set of antennas were fabricated and then used together with a custom synthetic aperture radar system and SAR imaging performed on a point target in an anechoic chamber. Imaging results are also discussed in this paper showing improvement in image output. The antenna and its connected SAR systems developed in this work are different from most previous work in that this work is utilizing circular polarization as opposed to linear polarization.

Internal power losses in lumped-element impedance matching circuits are formulated by means of Q factors of the elements and port impedances to be matched. Assuming that Q factors are relatively high, the above mentioned loss is expressed by a simple formula containing only the tangents of the impedances. The formula is a powerful tool for such applications that put emphasis on power efficiency as wireless power transfer. As well as the formulation, we illustrate some design examples with the derived formula: design of the least lossy L-section circuit and two-stage low-pass ladder. The examples provide ready-to-use knowledge for low-loss matching design.

This paper presents a wideband digital predistortion (DPD) architecture suitable for wideband wireless systems, such as IEEE 802.11ad/WiGig, where low oversampling ratio of the digital-to-analog converter (DAC) is a bottleneck for available linearization bandwidth. In order to overcome the bandwidth limitation in the conventional DPD, the proposed DPD introduces a complex coefficient filter in the DPD signal processing, which enables it to achieve asymmetric linearization. This approach effectively suppresses one side of adjacent channel leakages with twice the bandwidth as compared to the conventional DPD. The concept is verified through system simulation and measurements. Using a scaled model of a 2 GHz RF carrier frequency, the measurement shows a 4.2 dB advantage over the conventional DPD in terms of adjacent channel leakage.

This paper introduces a novel Direct Digital Frequency Synthesizer based on Complementary Dual-Phase Latch-Based sequencing method. Compared to conventional Direct Digital Frequency Synthesizer using Flip-Flop as synchronizing element, the proposed architecture allows to double the data sampling rate while trading-off area and Power Efficiency. Digital domain modulations can be easily implemented by using a Direct Digital Frequency Synthesizer. However, due to performance limitations, CMOS-based applications have been almost exclusively restricted to VHF, UHF and L bands. This work aims to increase the operation speed and extend the applicability of this technology to Multi-band Multi-standard wireless systems operating up to 2.7 GHz. The design features a 24 bits pipelined Phase Accumulator and a 14x10 bits Phase to Amplitude Converter. The Phase to Amplitude Converter module is compressed by using Quarter Wave Symmetry technique and is entirely made up of combinational logic inserted into 12 Complementary Dual-Phase Latch-Based pipeline stages. The logic is represented in the form of Sum of Product terms obtained from a 14x10 bits sinusoidal Look-Up-Table. The proposed Direct Digital Frequency Synthesizer is designed and simulated based on 65nm CMOS standard-cell technology. A maximum data sampling rate of 6.8 GS/s is expected. Estimated Spurious Free Dynamic Range and Power Efficiency are 61 dBc and 22 mW/(GS/s) respectively.

Near field communication (NFC) antennas are often lined with magnetic sheets to reduce performance degradation caused by nearby metal objects. Though amorphous sheets have a high permeability and are suitable magnetic sheets for lining, their magnetic loss is also high. Therefore, this paper suggests a technique of suppressing magnetic loss by modifying the shape of the sheet without changing its composition. The utility of the proposed technique was investigated in this study.

Magnet-less non-reciprocal metamaterial (MNM) synthesise artificial magnetic gyrotropy by metal ring resonator with unilateral component insertion. Clear advantage to natural magnetic material is full integrated circuit ingredient compatibility but still suffers from drawbacks of consumption power in active component and footprint of ring resonator. A new MNM structure by a varactor inserted figure of eight resonator is introduced, which enables reduction of active components by half and even smaller footprint to the original simple ring resonator structure in addition to frequency tunability.

This paper proposes a power supply voltage control technique, and demonstrates its effectiveness for eliminating the overkills and underkills due to the power supply characteristic difference between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method controls the static power supply voltage on the ATE system, so that the ATE can eliminate misjudges for the Pass or Fail of the DUT. The method for calculating the power supply voltage is also described. Experimental results show that the proposed method can eliminate 89% of overkills and underkills in delay fault testing with 105 real silicon devices. Limitations of the proposed method are also discussed.