Semiconductor technology is advancing toward the 2 nm generation, requiring breakthroughs in materials, device architectures, process technologies, and packaging. These innovations not only enhance performance but also enable progress in AI, communications, energy efficiency, and healthcare, while reinforcing semiconductors as strategic assets in global competition. Core technologies rooted in surface and interface science. This issue presents their status and prospects from diverse expert perspectives.

This study presents the development and application of synchrotron-based tools for evaluating EUV lithography components at the NewSUBARU synchrotron light facility. EUV multilayer optics and photomasks are analyzed using EUV reflectometers to assess reflectance and absorber material properties. High-intensity EUV irradiation enables durability testing and evaluation of hydrogen blister formation in mask materials. For photoresists, sensitivity, resolution, and electron yield are measured under EUV exposure, with a focus on materials that suppress line width roughness. The facility is also expanding into Beyond-EUV (BEUV) technologies, with measurement systems operating at a wavelength of 6.7 nm. As a platform for advanced lithography research, NewSUBARU plays a vital role in supporting next-generation semiconductor development and strengthening industry-academia collaboration in materials evaluation.

Atomic layer processes (ALP), including ALD, ALE, and ASD, are becoming essential for enabling 2 nm-generation ULSI interconnects, where conventional materials and processes face critical limitations. ALP offers atomically precise control over film thickness, composition, and selectivity, helping to address RC delay, reliability concerns, and alignment challenges. This article highlights recent progress and integration strategies for applying ALP to advanced BEOL structures for 2 nm era.

GAA (Gate All Around) FETs have been developed for 2 nm-generation logic devices. This paper discusses key etching challenges and technologies for the device, Si/SiGe nanosheet etching with H₂ gas chemistry using a Microwave ECR etching tool, reduced WFM (Work Function Metal) erosion and enhanced nano-space etching capability in WFM patterning through DC pulse technology, and HK (High-K)/WFM recess etching employing an ALE (Atomic-Layer Etching)-like approach with boron deposition control. Additionally, this paper demonstrates conformal ALE of Si₃N₄ in nanoscale spaces using a Dry Chemical Removal (DCR) tool equipped with an IR lamp.

Chiplet packaging technology is one of the important integration technologies for 2-nm generation advanced semiconductors. In this article, bonding and TSV (through silicon via) technologies, which are key factors of chiplet packaging technology for 2-nm generation advanced semiconductors are introduced.

After defining what “development,” “mass-production,” and “yield” mean in semiconductors, I revealed the strategies and current status of TSMC, Samsung, Intel, and Rapidus for 2 nm logic. As a result, I inferred that as of the second to third quarter of 2025, TSMC's 2 nm process is on the verge of ramping up mass production ; Samsung's 2 nm process and Intel's 18A process are in the late stage of development ; and Intel's 14A process and Rapidus's 2 nm process are in the early stage of development.