This paper proposes a concept of the adaptive asynchronous human machine system (-HMS) which maintains asynchronous periodic operations against user's actions for avoiding user intention. In order to find the dynamics of the operation period presented by -HMS, discrimination thresholds of the operation period were obtained by psychophysical experiment. According to the thresholds, three levels of fluctuation of the operation period were defined as ‘constant’, ‘unrecognizable’, and ‘recognizable’. Psychophysiological measurement was conducted on the performance of the synchronized key typing task by the three levels of the operation period. A synchronization error as performance index, the hemodynamic parameters as indices of autonomic nervous system's activity, and the amount of the senses as psychological indices were evaluated. As a result, monotonous feeling was eliminated without compromising the performance in case of `unrecognizable' fluctuations in the operation period presented by -HMS.

抄録全体を表示

An echocardiographic evaluation of right and left ventricular function during synchronous and asynchronous left heart device pumping was carried out in 20 mongrel dogs to establish the long term monitoring system as a non-invasive method.
The echo transducer was placed on the right ventricular epicardium directry or 1.5-2cm away from it, as the immersed method. The effects of LHB on heart rates, LVDd, LVDs, RVDd, RVDs and LVSV were measured and following results were obtained; 1) almost no changes of heart rates and RVD during sync. and ., 2) a significant decrease of LVDd and LVSV during both sinc. and . with good correlation to the bypass ratio, 3) no signifcant changes of these determinants between . and sync.
The results of this study demonstrate the usefulness of echocardiographic monitoring in the evaluation of a left heart assist device as a noninvasive, repeatable and reliable method.

抄録全体を表示

In this paper, we propose a design method to design asynchronous circuits with bundled-data implementation on commercial Field Programmable Gate Arrays using placement constraints. The proposed method uses two types of placement constraints to reduce the number of delay adjustments to fix timing violations and to improve the performance of the bundled-data implementation. We also propose a floorplan algorithm to reduce the control-path delays specific to the bundled-data implementation. Using the proposed method, we could design the asynchronous circuits whose performance is close to and energy consumption is small compared to the synchronous counterparts with less delay adjustment.

抄録全体を表示

1.はじめに
森林におけるGPS測位精度については様々な研究が行われてきたが，落葉樹林における測位精度の季節変化についての検証は，十分には行われていない。吉村ら(2003)は林内静止時におけるGPS測位精度の季節変化を調べ，樹冠下における測位精度の低下には，上空に覆う葉の影響よりも，樹幹や枝による短時間の信号遮断の影響が大きいと推測している。そこで本研究では，落葉広葉樹林内の定点において，開葉から落葉まで，毎週3時間のGPS測位を行うことによって，測位精度の季節変化を観察し，測位精度に影響を与える要因について検討を行った。
2.方法
試験は京都大学フィールド科学教育研究センター上賀茂試験地落葉広葉樹人工林分のGPS観測定点において，2003年5月2日から同年12月25日までの期間，週に一回の頻度で午前10時から午後1時まで測位を行った。観測地点を中心にした半径10mの円形プロットにおいて毎木調査を行ったところ，主要樹種はチャンチンモドキ，立木密度350本/ha，平均胸高直径37.4cm，平均樹高18.5m，胸高断面積合計51.5m²/haであり，一部に人工植栽された外来マツが含まれていた。使用した受信システムはハンディGPS受信機（Garmin社製GPS3+）および外部アンテナ（Motorola社製）で，およびgar2rnxを使用してパソコンにRINEXファイルを直接記録した。得られたデータを30分ごとのデータに分割し，京都大学GPS基準局データを基地局にして基線解析ソフト（LeicaGeosystem社製 SkiPro1.1）を用いて干渉測位およびコードディファレンシャル測位（以下，DGPS）を行い，測位誤差（平面方向）を求めた。定点座標の真値は二周波受信機および周辺の三角点を用いた三次元網平均により算出した。またRINEXファイルから，平均PDOPおよび平均信号強度，平均衛星捕捉数を求めた。マスク設定は基線解析時に仰角マスク（15度）のみ設定した。葉量の指標として，測位時にデジタルカメラ（Nikon社製CoolPix995およびFC-8）で全天写真を撮影し，LIA32ver.0.376β1を用いて仰角15度以上の部分について開空度を算出した。また同時にチャンチンモドキのフェノロジーを記録した。
3.結果と考察
(1)開空度の季節変化
開空度の季節変化およびフェノロジーを図-1a に示す。観測開始時に46.6%であったものが，夏期には21.1%となり，観測終了時には51.5%となった。結実は8月30日で，観測終了時にも落果しないものが多数見られたが，開空度への影響はほとんどなかった。
(2)測位精度の季節変化
干渉測位およびDGPSにおける測位誤差の推移を図-1b に示す。干渉測位はDGPSに比べ精度のばらつきが大きかった。干渉測位誤差と開空度とは弱い相関が認められた（R²=0.018, p=0.064）が，DGPS測位誤差と開空度とでは相関は見られなかった（p=0.363）。
(3)測位誤差に影響を与える要因
測位誤差に影響を与えている因子について検討するため，測位誤差を従属変数とした重回帰分析を行った（表-1）。その結果，DGPS，干渉測位のいずれの場合も捕捉衛星数および信号強度が測位精度に影響を与えていることが分かった。本試験では，開空度の上昇はむしろ測位精度を悪化させる傾向にあり，測位精度にはほとんど影響していなかった。
(4)開空度に影響される要因
開空度が変化することにより影響される要因について検討するため，相関分析を行った。もっとも相関の高かった信号強度と開空度の関係を図-2に示す。開空度が35%以下になると信号が劣化する傾向が見られた。
4.おわりに
上記の結果から，開空度の減少により信号強度が低下するが，干渉測位およびDGPSにおける測位精度を大きく劣化させるまでには至らず，むしろ捕捉衛星数の変化による影響の方が大きいことが明らかになった。ただし，感度が劣る受信システムを用いた場合や，移動中，あるいはより葉量の多い林分においては，信号劣化が測位精度に影響を与える可能性がある。今後，他の林分や受信システムでも試験を行う予定である。

抄録全体を表示

In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.

抄録全体を表示

Body representation is shaped by integrating information from various sensory modalities. This study investigated the relationship between age-related changes in the visuo-proprioceptive integration of body representation and interoceptive ability. Results showed that older adults demonstrated a greater proprioceptive drift than younger counterparts. Further, the results revealed that younger adults’ proprioceptive drift tended to diminish as time elapsed; conversely, older adults did not experience any reduction. No discrepancies were detected between age groups on any interoceptive abilities. However, all participants exhibited a significant positive correlation between their interoceptive sensibility and the degree of body position perception update. Therefore, it can be concluded that the higher their interoceptive sensibility, the more likely it is that participants experience body position perception update. These results suggest that interoceptive ability is associated with the update process of body position perception but does not explain the gap between age groups.

抄録全体を表示

In this paper, we propose a new method for measuring metastability in the mutual exclusion element (MUTEX) implemented on a Field Programmable Gate Array (FPGA). Our method uses fine-grained phase shifts of a digital clock manager to trigger Flip-Flops to generate concurrent inputs for a MUTEX. By dynamically adjusting the phase shift between two clock signals, we can force the MUTEX into a metastable state. The benefit of our approach is that it is easier to force the MUTEX become metastable compared to the conventional approach using two un-correlated signals. The experiments have been performed on a Xilinx Spartan-6 (XC6SLX9-4TQG144C).

抄録全体を表示

A modern system-on-chip (SoC) includes many heterogeneous IP components. Generally, a few embedded processors are integrated into SoCs. An asynchronous circuit design technique is employed to achieve low power/energy consumption. In this paper, we design an asynchronous embedded processor on FPGAs and analyze its possible benefits on commercial FPGAs. We use commercially available 65nm high-performance Virtex-5 and 45nm low-power Spartan-6 Xilinx FPGAs to show the impact on power consumption for the two different extreme cases. For the high performance Virtex-5, our asynchronous processor shows 36.8% lower power consumption when compared with its synchronous counterpart. On the other hand, the asynchronous processor consumes 25.6% more power in a low power Spartan-6 FPGA. However, through simple analysis and power simulation, we show that the event-driven nature of asynchronous circuits can further save power/energy even in the Spartan-6 FPGA.

抄録全体を表示

This paper proposes an ASIC design support tool set for non-pipelined asynchronous circuits with bundled-data implementation. This tool set consists of seven tools to automate design processes of bundled-data implementation such as the generation of design constraints, timing verification, and delay adjustment considering a given latency constraint. With the proposed design flow which combines the proposed tool set and commercial CAD tools, most of design processes from an RTL model is fully automated. In the experiments, to show the effectiveness of energy consumption in bundled-data implementation compared to synchronous counterpart, this paper synthesizes several circuits with a latency constraint which is generated from the synchronous counterpart with the minimum clock cycle time.

抄録全体を表示

This paper proposes a behavioral synthesis system for asynchronous circuits with bundled-data implementation. The proposed system is based on a behavioral synthesis method for synchronous circuits and extended on operation scheduling and control synthesis for bundled-data implementation. The proposed system synthesizes an RTL model and a simulation model from a behavioral description specified by a restricted C language, a resource library, and a set of design constraints. This paper shows the effectiveness of the proposed system in terms of area and latency through comparisons among bundled-data implementations synthesized by the proposed system, synchronous counterparts, and bundled-data implementations synthesized by using a behavioral synthesis method for synchronous circuits directly.

抄録全体を表示

This paper proposes a behavioral synthesis system for asynchronous circuits with bundled-data implementation. The proposed system is based on a behavioral synthesis method for synchronous circuits and extended on operation scheduling and control synthesis for bundled-data implementation. The proposed system synthesizes an RTL model and a simulation model from a behavioral description specified by a restricted C language, a resource library, and a set of design constraints. This paper shows the effectiveness of the proposed system in terms of area and latency through comparisons among bundled-data implementations synthesized by the proposed system, synchronous counterparts, and bundled-data implementations synthesized by using a behavioral synthesis method for synchronous circuits directly.

抄録全体を表示

We investigate the terminating grid exploration for autonomous myopic luminous robots. Myopic robots mean that they can observe nodes only within a certain fixed distance, and luminous robots mean that they have light devices that can emit colors. First, we prove that, in the semi-synchronous and asynchronous models, three myopic robots are necessary to achieve the terminating grid exploration if the visible distance is one. Next, we give fourteen algorithms for the terminating grid exploration in various assumptions of synchrony (fully-synchronous, semi-synchronous, and asynchronous models), visible distance, the number of colors, and a chirality. Six of them are optimal in terms of the number of robots.

抄録全体を表示

In this paper, a 16 times 16 low-power low-area asynchronous iterative multiplier is proposed. The multiplier diminishes 2 bits at a time with an iterative structure, to filter out the useless switching activities, we employ a finishing detector to dynamically detect the end of the computation and stop iteration ahead of schedule. Additionally, with the employment of finishing detectors, the proposed multiplier could provide a much faster average speed than synchronous approach. Post-layout simulation results show that the asynchronous multiplier offers up to 74% power reduction compared with the synchronous design. Simultaneously, the proposed design also exhibits a prominent area reduction compared with other non-iterative multiplier benefited from the iterative architecture.

抄録全体を表示

A high-speed rendering method for three-dimensional animated volume rendering in a CAVE visualization environment is developed. The proposed method accelerates the standard three-dimensional texture-slicing approach to volume rendering by making use of asynchronous data transfer with the pixel buffer object of graphics processors. The method enables stereoscopic animation of volume rendering at five frames per second for scalar data of 512³ grid points in a four-screen CAVE system.

抄録全体を表示

This paper presents a study of GALS (Globally-Asynchronous Locally-Synchronous) architecture multi-core processor design with asynchronous interconnects. While GALS is expected to reduce more power dissipation, it has not been the mainstream of LSI design yet, since there have been no mature design tools for asynchronous circuit design. For GALS design, we constructed a design flow based on general synchronous design tools, by specification of design constraints and configurations. Applying the design flow to an experimental multi-core processor GALS design including an asynchronous interconnect based on QDI (Quasi Delay Insensitive) model, we successfully obtained a netlist and layout, and proved that the flow works correctly, by netlist simulation with delay information back-annotated from the layout. Experimental results show the area, power and throughput of the asynchronous interconnect to indicate the impact by introducing GALS architecture instead of globally synchronous design.

抄録全体を表示

This paper presents a study of GALS (Globally-Asynchronous Locally-Synchronous) architecture multi-core processor design with asynchronous interconnects. While GALS is expected to reduce more power dissipation, it has not been the mainstream of LSI design yet, since there have been no mature design tools for asynchronous circuit design. For GALS design, we constructed a design flow based on general synchronous design tools, by specification of design constraints and configurations. Applying the design flow to an experimental multi-core processor GALS design including an asynchronous interconnect based on QDI (Quasi Delay Insensitive) model, we successfully obtained a netlist and layout, and proved that the flow works correctly, by netlist simulation with delay information back-annotated from the layout. Experimental results show the area, power and throughput of the asynchronous interconnect to indicate the impact by introducing GALS architecture instead of globally synchronous design.

抄録全体を表示

A 10 Gbps transmitter bridge chip including four data lanes, which increases the bandwidth using an 8-to-1 serialization, is proposed for a field-programmable gate array (FPGA)-based frame generator to support the protocol of the D-PHY version 1.2 for the mobile industry processor interface (MIPI) display serial interface (DSI).

抄録全体を表示

File systems make use of the buffer cache to enhance their performance. Traditionally, part of DRAM, which is volatile memory, is used as the buffer cache. In this paper, we consider the use of of Non-Volatile RAM (NVRAM) as a write cache for metadata of the file system in embedded systems. NVRAM is a state-of-the-art memory that provides characteristics of both non-volatility and random byte addressability. By employing NVRAM as a write cache for dirty metadata, we retain the same integrity of a file system that always synchronously writes its metadata to storage, while at the same time improving file system performance to the level of a file system that always writes asynchronously. To show quantitative results, we developed an embedded board with NVRAM and modify the VFAT file system provided in Linux 2.6.11 to accommodate the NVRAM write cache. We performed a wide range of experiments on this platform for various synthetic and realistic workloads. The results show that substantial reductions in execution time are possible from an application viewpoint. Another consequence of the write cache is its benefits at the FTL layer, leading to improved wear leveling of Flash memory and increased energy savings, which are important measures in embedded systems. From the real numbers obtained through our experiments, we show that wear leveling is improved considerably and also quantify the improvements in terms of energy.

抄録全体を表示