A Decision Diagram Machine (DDM) is a special-purpose processor that has special instructions to evaluate a decision diagram. Since the DDM uses only a limited number of instructions, it is faster than the general-purpose Micro Processor Unit (MPU). Also, the architecture for the DDM is much simpler than that for an MPU. This paper presents a packet classifier using a parallel EVMDD (
k) machine. To reduce computation time and code size, first, a set of rules for a packet classifier is partitioned into groups. Then, the parallel EVMDD (
k) machine evaluates them. To further speed-up for the standard EVMDD (
k) machine, we propose the prefetching EVMDD (
k) machine which reads both the index and the jump address at the same time. The prefetching EVMDD (
k) machine is 2.4 times faster than the standard one using the same memory size. We implemented a parallel prefetching EVMDD (
k) machine consisting of 30 machines on an FPGA, and compared it with the
Intel's
Core
i
5
microprocessor running at 1.7GHz. Our parallel machine is 15.1-77.5 times faster than the Core i5, and it requires only 8.1-58.5 percents of the memory for the Core i5.
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