Design Principle and Static Coding Efficiency of STT-coder

Abstract

We have proposed a fast and simple binary arithmetic coder STT-coder, in which arithmetic operation of dividing the probability interval can be done using a state transition table. In this paper, we report the design principle of STT-coder having a 6-bit interval register and evaluation of its coding performance, which include examination about a parameter “offset” to optimize the number of offsets as well as their values. We also examined the assignment of LPS width to a valid probability interval to improve the coding efficiency of STT-coder.