Article ID: 2017XBL0056
This paper describes the implementation and design of interface for peripheral component interconnect express (PCIe) interconnect and memory in a complex system on chips (SoC). PCIe bus traffic is made of a series of PCIe bus transactions. The direction of the data will be from initiator to completer (for write transaction) or vice-versa (for read transaction). The interface will read the command of the master and send corresponding response to the master. The major objective of the project is performance verification of SoC on a dedicated channel between PCIe end point and memory using performance models. We are using direct memory access (DMA) type of requests and bandwidth is measured at bottleneck for different PCIe generations, lane configurations and payloads. Bandwidth obtained is being compared with theoretical peak bandwidth calculated.