Proceedings of JIEP Annual Meeting
The 20th JIEP Annual Meeting
Session ID : 23B-05
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Host: Japan Institute of Electronics Packaging

Develoment of method for designing controlled impedance vias
*Satoshi Ikeda, Kenichi Higashiura, Akihiro Tanaka
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Keywords: impedance, PCB, design
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[in Japanese]
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© 2006 by The Japan Institute of Electronics Packaging
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