IEICE ESS Fundamentals Review
Online ISSN : 1882-0875
ISSN-L : 1882-0875
Proposed by VLD
LSI Design Technology for Ultra-low Voltage Operation
Kimiyoshi USAMI
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JOURNAL FREE ACCESS

2017 Volume 10 Issue 3 Pages 195-205

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Abstract
In LSIs for sensor nodes or medical devices, energy dissipation is minimized by reducing the supply voltage to a value near the threshold voltage (Vt) of MOS transistors or even lower than Vt. Design issues in these LSIs are different from those of LSIs operating at a normal voltage. In addition to the difficulty in achieving stable operation, the circuit performance is significantly affected by process and temperature variations. This paper focuses on the logic and memory circuits used in microcontrollers or SoCs operating at ultra-low voltages, and surveys major issues and design techniques. As new topics, two key enablers for ultra-low-voltage operation are also described: a fully depleted silicon-on-insulator (FD-SOI) device and the standard cell memory (SCM) approach.
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© 2017 The Institute of Electronics, Information and Communication Engineers
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