2023 Volume 16 Issue 4 Pages 272-288
The number of transistors per semiconductor chip has consistently and exponentially increased over the past 50 years. Therefore, a larger amount and more complex functions can be implemented in the chip. In order to tackle this trend, design methodologies have evolved from being schematic-based to being more abstract language-based, and design productivity has been increased through the reuse of design assets and the adoption of standard bus interfaces. Similarly, functional verification can no longer keep up with conventional verification methods, mainly because verification coverage and productivity issues have become critical. In this paper, verification techniques, methodologies, and the history of standardization to resolve these verification issues are described. On top of these, new verification items that arise with asynchronous and low-power consumption designs, as well as issues that require more functional verification effort, such as security measures and compliance with functional safety standards and their countermeasures, are descussed. Verification technologies that have been developed in line with leading software development technologies and look ahead to the possibilities for future advancements in verification technologies.
