Abstract
This paper discusses High-Level Synthesis (HLS), which reads C or C++ behavioral descriptions and generates a register-transfer level description for ASIC or FPGA. First, the LSI design process and the history of LSI design automation are introduced, and the reason why design processes were automated with the increasing size of LSI is discussed. Next, the fundamental processes in HLS are explained. The advantages of HLS are higher design efficiency, performance, reliability, and reusability. This paper illustrates how and why HLS provides such advantages. This paper also discusses the performance of FSMD, which is the target architecture of HLS and consists of a finite-state machine and a datapath in contrast to a CPU. It has taken many years to create a practical commercial HLS tool since its prototype. This is because a practical HLS tool requires a variety of optimizing techniques. This paper introduces some of the important techniques. Then, the application of HLS to not only data-dominant circuits but also control-intensive circuits is explained. Then, the difference between the C description for hardware and software is illustrated. Finally, recent HLS techniques for FPGAs and the new application area “FPGAs and C-based HLS” are explained.
