Hardware acceleration of a basis function network

Abstract

Hardware acceleration of a basis function network which has a good spatial approximation ability is described in this paper. By using pipe-line architecture and simplifying the algorithm, high speed operation (10 times as fast as the previous model) has been achieved. We implement the proposed system to an FPGA and confirm the performance with computer simulations (delay-simulations). By comparing the previous systems, the validity of the proposed system is discussed.