IEEJ Transactions on Electronics, Information and Systems
Online ISSN : 1348-8155
Print ISSN : 0385-4221
ISSN-L : 0385-4221
Letter
A 1-Dimensional Chaotic IC Designed by SI Techniques
Kei EguchiHongbing ZhuToru TabataFumio UenoTakahiro Inoue
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2003 Volume 123 Issue 9 Pages 1663-1664

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Abstract
In this paper, a VLSI chip of a discrete-time chaos circuit realizing a tent map is reported. The VLSI chip is fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC). A simple structure enables us to realize the circuit with 10 MOSFET’s and 2 capacitors. Furthermore, the circuit which is designed by switched-current (SI) techniques can operate at 3V power supply. The experiment concerning the VLSI chip shows that the proposed circuit is integrable by a standard 1.2 μm CMOS technology.
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© 2003 by the Institute of Electrical Engineers of Japan
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