IEEJ Transactions on Electronics, Information and Systems
Online ISSN : 1348-8155
Print ISSN : 0385-4221
ISSN-L : 0385-4221
<Information Processing, Software>
Implementation and Evaluation of Improvement in Parallel Processing Performance on the Cluster Using Small-Scale SMP PCs
Takafumi FukunagaHidenori Umeno
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2008 Volume 128 Issue 12 Pages 1842-1851

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Abstract
Various techniques that improve performance on SMP Clusters have been studied. Most of them use special hardware and non standard protocol, tending to raise their total cost and to spoil their flexibility. We propose CPU_NIC method which improves parallel performance on small-way SMP PC cluster only by loading driver. A proposal system is realizable with non intelligent switches. A proposal method uses the same number of NICs as CPUs and relates CPU and NIC with one to one. The transmitting frames are outputted from NIC related with execution CPU. Thus, by fixing transmitting NIC for every CPU, the sack frames which are easy to generate in communication load sharing to two or more NIC is able to be reduced and parallel processing performance is able to improve. As a result of measuring using NPB benchmarks on SMP cluster which consists of four SMP PCs, FT, MG and CG become 1.12 times, 1.29 times and 3.06 times faster respectively by proposal method, as compared with ordinary system without this method.
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© 2008 by the Institute of Electrical Engineers of Japan
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