Design Technology of stacked NAND type 1-transistor FeRAM

Abstract

Design technology of stacked NAND type 1-transistor FeRAM has been described. With 39nm design rule feasibility study of 1Tbit memory focused on cell array structure and core circuit has been investigated. 64 layer 8k×8k stacked SGT memory cell array structure and the double ended row and column decoder with SGT have been newly introduced.
From the estimation of wordline and bitline delay time this structure enables to reduce the delay time of core circuit to 5ns. Stacked NAND type 1-transistor FeRAM is a promising candidate for realizing fast access time of 50ns.