Abstract
PLL-MSC (Phase Locked Loop Motor Speed Control) systems can completely reject speed error and steady-state phase error for constant-speed input signals. However, it is not usually applied to systems with inputs including acceleration, because they have poor tracking speed and strange pull-in behavior.
In the field of radio communication, “dual-loop PLL” is very effective for such signals. It can not only enable high-speed tracking, but also cancel phase error.
In the digital implementation of the PLL-MSC, it can achive easily by inserting loop filters into both feed back paths, and employed a special adder in PWM to implement loop addition for the two phase detector outputs. The scheme was implemented by programming an FPGA, and satisfiable results were obtained.
