IEEJ Transactions on Electronics, Information and Systems
Online ISSN : 1348-8155
Print ISSN : 0385-4221
ISSN-L : 0385-4221
<Softcomputing, Learning>
FPGA Implementation of Discrete-Time Neuronal Network for Dynamic Image Segmentation
Ken'ichi FujimotoMio MusashiTetsuya Yoshinaga
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2011 Volume 131 Issue 3 Pages 604-605

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Abstract
We have developed a discrete-time dynamical system for dynamic image segmentation. It consists of a global inhibitor and modified chaotic neurons that can generate oscillatory responses. Dynamic image segmentation is performed using its oscillatory responses. This letter presents an implementation of our system in a field programmable gate array (FPGA) device and a successful result of dynamic image segmentation.
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© 2011 by the Institute of Electrical Engineers of Japan
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