Design Method for Stacked FeRAM with Oxide-Channel Transistor

Abstract

Design method for stacked FeRAM with oxide-channel transistor has been newly proposed. Using this architecture without sacrificing the reliability of the ferro-electric thin film, both high-speed competitive DRAM and low-cost more than 1 layered Flash memory can be successfully realized. For the case of µ=20cm²/vs stacked NAND structure is available. For the case of µ=0.2cm²/vs stacked NOR structure is effective.