IEEJ Transactions on Electronics, Information and Systems
Online ISSN : 1348-8155
Print ISSN : 0385-4221
ISSN-L : 0385-4221
<Electrical and Electronic Circuit, LSI>
Design Technology of Stacked NAND Type FeRAM with 2 Transistor Type Memory Cell
Koichi SuganoShigeyoshi Watanabe
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2011 Volume 131 Issue 7 Pages 1327-1336

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Abstract
Design method of stacked NAND type FeRAM with 2-transistor type memory cell has been newly proposed. With newly introduced WL voltage generator which enables to compensate drain current variation caused by mis-alignment of the ferro-electric film removal mask 4F2 small cell size has been successfully realized. 32 stage of stacked NAND type FeRAM is a promising candidate for realizing high reliability compared with the conventional stacked NAND type 1-transistor FeRAM.
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© 2011 by the Institute of Electrical Engineers of Japan
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