Abstract
Electronic devices handling confidential information, such as IC cards, are secured by encrypting data. The encryption standard, which has been widely diffused in recent years, is certified that its decryption is computationally impossible. However, although an encryption algorithm is theoretically secured, when the algorithm is incorporated into hardware, confidential information about the algorithm could be improperly specified by analyzing power consumption that is generated during cipher processing. Therefore, when an encryption algorithm is incorporated into hardware, it is important to evaluate the resistance against power analysis attacks in the design stages. This paper proposes a new vulnerability evaluation for power analysis attacks. The proposed method can not only achieve a high-speed, highly accurate verification but also quantitatively evaluates a weak part. Experimental results prove the validity of the proposed tamper resistant analysis method.
