Proposal of a Method to Improve Linearity of Time Analog to Digital Converter

Abstract

The Time Analog to Digital Converter (TAD) is a compact, high-resolution A/D converter. TAD uses a Ring Delay Line (RDL). In this paper, we have proposed a method to improve the linearity of TAD using a current-controlled RDL. Simulation showed about 80 percent improvement of linearity compared to the original TAD. Optimum design of proposed circuit and detailed comparison between original TAD and current-controlled TAD are necessary for future work.