Coupling Capacitance Extraction between TSVs in 3D ICs Using Inverse of Inductance Matrix

Abstract

For extracting coupling capacitances between through silicon vias (TSVs) in three dimensional integrated circuits (3D ICs), a method using the inverse of inductance matrix was investigated. We clarify the accuracy of the method by various structures such as same/different diameters and regular/irregular arrangements. When a huge number of TSVs were used, the inductance matrix gets very large. Therefore, we propose a method for getting coupling capacitances with reasonable accuracy by a small inductance matrix when a lot of TSVs with the same diameter were located regularly.