An Architecture of Real Coded Genetic Algorithm Processor

Abstract

Real Coded Genetic Algorithm (RCGA) is one of evolutionary algorithm for handling real-valued vector. The RCGA is much better than conventional GA handling with bit strings as genotype. Various dedicated hardware for GA have been proposed for speedup or the applications of evolvable hardware. However, many of these hardware based on the bit strings GA or the compact GA. Therefore, there are few reports of RCGA hardware. In this paper, we propose an architecture of RCGA processor. The proposed processor conform to the Just Generation Gap (JGG) as a generation alternation model of RCGA. In addition, the processor is implemented the Real coded Ensemble Crossover (REX). One of the features of proposed processor is that the REX circuit can be implemented with small circuit scale because the circuit resources effectively shared such as arithmetic units. Furthermore, the second feature is to evaluate the offspring using by the soft macro CPU. Thus, the versatility is enhanced because the evaluation function that depend on problems can change by rewriting of software. Moreover, they are implemented in parallel for speeding up. The proposed processor is expected in embedded field applications because of it can be implemented in one chip FPGA.