Stochastic TDC Architecture with Self-Calibration and its RTL Verification

Abstract

A time-to-digital converter (TDC) based on stochastic process and statistics theory is presented. This architecture utilizes the stochastic variation in CMOS process positively for fine time resolution. It needs a large number of flip-flops for statistics but advanced fine CMOS technology can realize it. The self-calibration technique using the histogram method is applied to compensate the nonlinearity due to the circuit characteristics variation as well as timing skew by layout and routing. The proposed TDC can be implemented with full digital circuit, which is suitable as nano-CMOS mixed-signal circuit. Register-Transfer-Level (RTL) simulation is conducted to validate the operation principle. RTL verification results indicate that the proposed stochastic architecture with self-calibration feature can realize a linear TDC with sub-picosecond time resolution.