2020 Volume 140 Issue 2 Pages 194-203
C-2C D/A converters (DAC) can be designed with fewer unit capacitors than binary weighted capacitive DAC (CDAC), which are advantages in power consumption, operating speed, and circuit area. However, in applications with medium or higher resolution, it needs larger circuit area because an accurate non-integer capacitance ratio is required in order to compensate the influence of the parasitic capacitance at the floating node. In this paper, by configuring C-2C DAC with only a simple integer capacitance ratio, the proposed circuit can be achieved with a smaller circuit area than split CDAC in 9-bit or higher. It also can compensate the variation of parasitic capacitance at floating node by applying the conventional digital correction technique.
The transactions of the Institute of Electrical Engineers of Japan.C
The Journal of the Institute of Electrical Engineers of Japan