IEEJ Transactions on Electronics, Information and Systems
Online ISSN : 1348-8155
Print ISSN : 0385-4221
ISSN-L : 0385-4221
<Electrical and Electronic Circuit, LSI>
Design and Verification of Ultra-small Processor with Specializes Binarized Neural Network
Tomokazu MasubuchiYuya ItoNorio TsudaKeishiro Goshima
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2021 Volume 141 Issue 2 Pages 165-171

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Abstract

A lot of multiplication circuits and a large-scale memory are required to operate a neural network. However, it is also necessary to use a low-power consumption and small-scale processor with a neural network for an embedded image-processing system. A binarized neural network (BNN) operating on the basis of the binary operation method is one of the candidates for solving such problems because the multiplication circuit is unnecessary, and a relatively small memory is required. In this study, an ultrasmall processor was designed with a specialized BNN based on the processor with a very small area for function, “Pilaf.” The processor designed is called “Pulin,” in which a control circuit is added that can access a large memory area and an image-processing arithmetic circuit. Despite the addition of some circuits, the design of Pulin demonstrates the same chip area as that of Pilaf because the architecture and the state machine are optimized. In addition, the processing time taken in the case of the neural network execution was reduced to approximately half that of the conventional processor. In addition, a large-scale integration (LSI) circuit was fabricated, and the delay time and operation speed of Pulin were analyzed using an LSI tester.

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© 2021 by the Institute of Electrical Engineers of Japan
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