Impact of the Device Size and N-type Isolation Layer Voltage on the Negative Input Withstand Capability of Fully Isolated nLDMOS

Abstract

This paper presents the negative drain input measurements of fully isolated nLDMOS which is fabricated by a low-cost process without any additional epitaxial growth. The critical drain current which causes the parasitic PNP activation is proposed as the index of the negative drain input withstand capability. The device size dependence measurements show that the negative drain input withstand capability decreases as the internal LDMOS area increases which is surrounded by the n-type isolation layer electrode. And, the bias application measurements to n-type isolation layer show that the trade-off relation between the anomalous substrate leakage and the parasitic PNP activation; that is, the higher applied bias suppresses the parasitic PNP activation but makes the anomalous substrate leakage larger.