マルチエピ法及びトレンチ埋め戻しエピ法で作製した1.2 kV耐圧SiC SJ-MOSFETの性能比較

染谷 満; 大薗 国栄; 紀 世陽; 俵 武志; 森本 忠雄; 加藤 智久; 児島 一聡; 原田 信介

doi:10.1541/ieejeiss.144.257

Comparison of 1.2 kV SiC Superjunction MOSFETs Formed by Multi-epitaxial Growth and Trench-filling Epitaxial Growth

Mitsuru Sometani, Kunihide Oozono, Shiyang Ji, Takeshi Tawara, Tadao Morimoto, Tomohisa Kato, Kazutoshi Kojima, Shinsuke Harada

Author information

Mitsuru Sometani
Advanced Power Electronics Research Center (ADPERC), National Institute of Advanced Industrial Science and Technology (AIST)
Kunihide Oozono
Advanced Power Electronics Research Center (ADPERC), National Institute of Advanced Industrial Science and Technology (AIST)
Shiyang Ji
Advanced Power Electronics Research Center (ADPERC), National Institute of Advanced Industrial Science and Technology (AIST)
Takeshi Tawara
Advanced Power Electronics Research Center (ADPERC), National Institute of Advanced Industrial Science and Technology (AIST)
Tadao Morimoto
Advanced Power Electronics Research Center (ADPERC), National Institute of Advanced Industrial Science and Technology (AIST)
Tomohisa Kato
Advanced Power Electronics Research Center (ADPERC), National Institute of Advanced Industrial Science and Technology (AIST)
Kazutoshi Kojima
Advanced Power Electronics Research Center (ADPERC), National Institute of Advanced Industrial Science and Technology (AIST)
Shinsuke Harada
Advanced Power Electronics Research Center (ADPERC), National Institute of Advanced Industrial Science and Technology (AIST)

Keywords: SiC, SJ-MOSFET, trench-filling epitaxial growth, static and dynamic characteristics

JOURNAL RESTRICTED ACCESS

2024 Volume 144 Issue 3 Pages 257-262

DOI https://doi.org/10.1541/ieejeiss.144.257

Details

Abstract

We compared static and dynamic characteristics of a 1.2 kV-Class SJ-MOSFET fabricated by the multi-epitaxial growth (ME) method and the trench-filling epitaxial growth (TFE) method, which is expected to have a lower process cost. Comparably low specific on-resistance and switching losses were observed for the SJ-MOSFETs fabricated by both methods.

Corresponding author

Register with J-STAGE for free!