A 2.8V Input Amplitude CMOS SAR ADC with 0.7V Supply Voltage

Abstract

This paper presents a 0.7V 12-bit 1.5MS/s SAR ADC incorporates an input amplitude attenuation architecture. To sample large amplitude input signals that exceed the supply voltage (V_in>V_DD), a modified bootstrapped switch architecture is proposed, which enhances the dynamic performance of the analog signal sampling switch. The proposed bootstrapped switch is utilized to construct a novel sample-and-hold (S/H) circuit that serves as the front-end for ADCs operating at low supply voltages while tolerating large amplitude input signals. The SAR ADC, which includes this novel S/H circuit, is in 65nm SOTB CMOS technology. It achieves a simulated SNDR of 65.71dB, a SFDR of 81.33dB and an ENOB of 10.62 bits with a full-scale input amplitude of V_{in_pp}=2.8V (peak-to-peak voltage) at 0.7V supply voltage V_DD.