A Neural Network Parallel Algorithm for One-Dimensional Gate Assignment Problems

Abstract

A near-optimum parallel algorithm for solving the one-dimensional gate assignment problem is presented in this paper where the problem is NP-hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n x n processing elements based on the artificial two-dimensional maximum neural network for (n+2)-gate assignment problems. Our algorithm has discovered the improved solutions in the benchmark problems over the best existing algorithms. The proposed approach is applicable to other VLSI layout problems such as the PLA (Programable Logic Array) folding problem.