Abstract
In this paper, we propose a system bus arbitration method suited for composing processor for packet change. This arbitration method has the following features: (1) low arbitration overhead, (2) high performance bus throughput, and (3) only a few number of arbitration signal lines requiring hardware on a small scale. Arbitration architecture provides one signal line for connecting the processors of each peripheral channel in a ring and circulates a 1-bit token among them. Also, in situations where the number of peripheral channels increases, we consider dividing the channels into multiple groups and propose an independent bus composition method designed to reduce the packet waiting times. The characteristics of the proposed method are examined by constructing and analyzing a Markovian model of the system. Finally, we verified the accuracy of analysis by comparing the results against simulation and use these results in discussing the best divisions of channels in terms of packet delay.
