νMOS Cellular-Automaton Circuit for Picture Thinning and Shrinking

Abstract

This paper proposes the circuit construction for implementing cellular-automaton LSIs. A cellular automaton is a parallel and distributed architecture suitable for high-speed image processing. To develop cellular-automaton LSIs, we must first create an unit cell circuit that can materialize cell-cell interaction rules in small-sized circuit construction. We propose constructing the cell circuits that uses νMOS FET devices. The template matching is implemented by combining multi-input νMOS circuits and inverters. We design the cell circuit for picture thinning and shrinking, and analyze its operation using a circuit simulator. A high-speed operation up to 100-MHz clock frequency can be obtained.