Abstract
In recent years, a very high-speed divider is required in real-time applications of digital signal processing and robot control and so on. In this paper, a high-speed divider based on high-radix division with selection function is proposed. To clear up problems for using high-radix, this divider uses a new technique which performs in parallel the operations in several quotient-digits. By using restoring division, this architecture can easily select partial remainder by each borrow output from MSB. Then, we propose borrow-save and BLA (Borrow Look-Ahead) as a new fast method of subtraction. Moreover the delay time of the proposed divider is calculated in terms of a delay of one unit such as NAND gate. Finally, by using PARTHENON, a CAD (Computer Aided Design) system for VLSI, this divider is designed and evaluated. As a result, we show that the proposed radix-X divider becomes about log2X times as fast as the radix-2 divider using borrow-save and BLA method.
