Abstract
For a true random number generator (TRNG) on an FPGA, the use of a pair of clocking elements has an advantage of minimal usage of its logic elements. This paper presents a novel high-speed TRNG for recent Xilinx FPGAs using their clocking elements called mixed-mode clock managers (MMCMs). By following the proposed parameter selection methods, both better randomness and higher throughput of generated bitstrings can be achieved. According to our evaluation on an Artix-7 FPGA with the most promising sets of parameters, 38.2% (42 out of 110) of the sets passed AIS-31 Procedure B, which means that an appropriate parameter set can be found by ten or less trials with more than 99% probability. The average throughput of them was 2.44 Mbit/s, which was comparable to recent FPGA-based TRNGs. An initial prototype of dynamic reconfiguration of the parameters is also presented in this paper.
