A Light-weight Random Number Generation for Tamper-resistant AES Circuit

Abstract

Various countermeasures have been proposed to reduce the characteristics that leak cryptographic keys from side-channel information such as power consumption and electromagnetic radiation. However, in the case of cryptographic processing with dedicated circuits, introducing high-quality random number generators lead to an increase in area cost of circuit implementation. Focusing on the parallel S-box implementation of AES, this paper proposes a novel circuit design that achieves improved tamper resistance while mitigating the increase in circuit area by reusing the existent S-boxes temporally and spatially.