a-Si Gate Driver designs for low power AMLCD operation

Keitaro Yamashita; Toshiya Inada; Steven Deane; Paul Collins; Satoshi Kawata; Yasuyuki Onda; Masahiro Yoshiga; Jason Hector; Masahide Inoue

doi:10.11185/imt.2.1

Hardware and Devices

a-Si Gate Driver designs for low power AMLCD operation

Keitaro Yamashita, Toshiya Inada, Steven Deane, Paul Collins, Satoshi Kawata, Yasuyuki Onda, Masahiro Yoshiga, Jason Hector, Masahide Inoue

Author information

Keywords: Amorphous silicon TFT, Gate Driver, Low Power Consumption, Partial Scanning, Shift Register, Long Lifetime

JOURNAL FREE ACCESS

2007 Volume 2 Issue 1 Pages 1-5

DOI https://doi.org/10.11185/imt.2.1

Details

Abstract

We have developed two 1.8" QVGA (222dpi) transflective a-Si AMLCDs with integrated gate drivers. One is optimized for a very low power normal operating mode. The other can switch to an arbitrary partial scan mode. Gate driver integration results in narrow, symmetric margins, reduced cost, and fewer interconnections. Also, we minimized the number of connections to the display while retaining some to achieve very significant power reduction.

Corresponding author

Register with J-STAGE for free!