Abstract
We investigated parallel image compression circuits suitable for integration in high-speed CMOS image sensors. We compared the coding efficiency and hardware complexity of several image compression algorithms that use 2-D DCTs using simulation and logic synthesis, and found that using 4×4 point 2-D DCT-based coding methods reduced hardware complexity and improved coding efficiency. We developed a parallel processing architecture for on-sensor image compression that use a processing element array and a data-buffering scheme for parallel data-output. We constructed a prototype 256 × 256 pixel high-speed CMOS image sensor chip that integrates 16 image compression-processing elements and uses 0.25-μm CMOS technology. The area of the image compression circuits is 80% of the image array with 15 μm square pixels. The entire chip could be operated at a clock frequency of 53.6 MHz, and high-speed images compressed by a factor of four could be read out at 10,000 fps using a 32-bit parallel bus.
