Information and Media Technologies
Online ISSN : 1881-0896
ISSN-L : 1881-0896
Hardware and Devices
Test and Design-for-Testability Solutions for 3D Integrated Circuits
Krishnendu ChakrabartyMukesh AgrawalSergej DeutschBrandon NoiaRan WangFangming Ye
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2014 Volume 9 Issue 4 Pages 386-403


Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. Test techniques and design-for-testability (DfT) solutions for 3D ICs are now being studied in the research community, and experts in industry have identified a number of hard problems related to the lack of probe access for wafers, test access in stacked dies, yield enhancement, and new defects arising from unique processing steps. We describe a number of testing and DfT challenges, and present some of the solutions being advocated for these challenges. Techniques highlighted in this paper include: (i) pre-bond testing of TSVs and die logic, including probing and non-invasive test using DfT; (ii) post-bond testing and DfT innovations related to the optimization of die wrappers, test scheduling, and access to dies and inter-die interconnects; (iii) interconnect testing in interposer-based 2.5D ICs; (iv) fault diagnosis and TSV repair; (v) cost modeling and test-flow selection.

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© 2014 Information Processing Society of Japan
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