IPSJ Transactions on System LSI Design Methodology
Online ISSN : 1882-6687
ISSN-L : 1882-6687
A Logic Optimization Method by Eliminating Redundant Multiple Faults from Higher to Lower Cardinality
Peikun WangAmir Masaud GharehbaghiMasahiro Fujita
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2020 Volume 13 Pages 35-38


In this paper, we propose a logic optimization method to remove the redundancy in the circuit. The incremental Automatic Test Pattern Generation method is used to find the redundant multiple faults. In order to remove as many redundancies as possible, instead of removing the redundant single faults first, we clear up the redundant faults from higher cardinality to lower cardinality. The experiments prove that the proposed method can successfully eliminate more redundancies comparing to the redundancy removal command in the synthesis tool SIS.

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© 2020 by the Information Processing Society of Japan
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